PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP Programming

Transcription

1 PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP Programming Maxime Pelcat, Karol Desnos, Julien Heulot Clément Guy, Jean-François Nezan, Slaheddine Aridhi EDERC 2014 Conference, Milan, September 11 th 1

2 Transistors/chip x2 every 18 months Source: Hardware-dependent Software, Ecker, et. al 2

3 Lines of code/chip x3.5 every 18 months Transistors/chip x2 every 18 months Source: Hardware-dependent Software, Ecker, et. al 3

4 Lines of code/chip x3.5 every 18 months Transistors/chip x2 every 18 months Lines of code/day +25% every 18 months Source: Hardware-dependent Software, Ecker, et. al 4

5 Lines of code/chip x3.5 every 18 months Transistors/chip x2 every 18 months Software Productivity Gap Lines of code/day +25% every 18 months Source: Hardware-dependent Software, Ecker, et. al 5

6 Typical Single DSP Environment INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES C/C++ Algorithm Code Compiler Program Command Line Options Simulator + Debugger + Profiler OS Core (s) 6

7 Multicore DSP Rapid Prototyping Functional Algorithm Model + Code Rapid Prototyping Program Program Program Program Deployment Constraints + Options Architecture Model Simulator + Debugger + Profiler OS Core 1 OS Core 2 7

8 Reduce Software Productivity Gap In early design phases: Metrics Design parallel algorithms Automatic mapping and scheduling Predictable time and memory choose the right algorithm and hardware 8

9 Reduce Software Productivity Gap In late design phases: Rapid Prototyping Automatic multi-core speedup Inter-core communication Guaranteed Deadlock-freeness 9

10 Reduce Software Productivity Gap For migration to a new hardware Seamless porting to a new architecture Legacy code reuseability Portable performance Dataflow modelling can help 10

11 PREESM for C6678 INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Algo dataflow + C Code Program Program Program Program PREESM Multiple C Programs Scenario Archi Model PREESM Simulator + CCS Debugger and Profiler SYS/ BIOS C66 C6678 SYS/ BIOS C66 11

12 Algo dataflow: PiSDF INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Read 1 Size Size Size Size Filter Size Display K. Desnos, M. Pelcat, J.-F. Nezan, S. S. Bhattacharyya, S. Aridhi PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Reconfiguration, SAMOS XIII 12

13 PiSDF Size Read 1 Size Size Size Size Filter Size Display K. Desnos, M. Pelcat, J.-F. Nezan, S. S. Bhattacharyya, S. Aridhi PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Reconfiguration, SAMOS XIII 13

14 back feed in out INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES PiSDF Size Read C Code 1 Size Size Size Size Filter Size Size Display C Code N Size Size Size/N Size/N Kernel Size/N Size/N Size Size K. Desnos, M. Pelcat, J.-F. Nezan, S. S. Bhattacharyya, S. Aridhi PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Reconfiguration, SAMOS XIII 14

15 back feed in out INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES PiSDF Size Read C Code 1 Size Size Size Size Filter Size Size Display C Code N Size Size Size/N Size/N Kernel C Code Size/N Size/N Size Size K. Desnos, M. Pelcat, J.-F. Nezan, S. S. Bhattacharyya, S. Aridhi PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Reconfiguration, SAMOS XIII 15

16 Algo dataflow: PiSDF INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES PiSDF MoC is: Hierarchical & Compositional Statically parameterizable Dynamically reconfigurable PiSDF fosters: - Predictability - Parallelism - Lightweight runtime overhead - Developer-friendliness K. Desnos, M. Pelcat, J.-F. Nezan, S. S. Bhattacharyya, S. Aridhi PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Reconfiguration, SAMOS XIII 16

17 Archi: System-Level Archi. Model Representing contentions as TDMA core1 TMS320C6678 core5 core2 core3 core4 MSMC 16 GB/s DDR3 5.3 GB/s core6 core7 core8 17

18 PREESM: Multicore Scheduling Scheduling based on latency and load balancing 18

19 PREESM: Multicore Scheduling Scheduling based on latency and load balancing 19

20 PREESM: Multicore Scheduling Scheduling based on latency and load balancing core1 core2 core3 core4 20

21 PREESM: Memory Bounds INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Bounding the memory needs of an application graph to: - Evaluate the memory requirements - Adjust the size of architecture memory - Assess the optimality of a memory allocation Insufficient memory Possible allocated memory Wasted memory 0 Lower Bound Upper Bound Available Memory 21

22 PREESM: Prototype Code Generation A B C D E o1 o2 A B C D E o1 Actor A Actor B Actor D o2 Actor C time Actor E 22 22

23 PREESM Features INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Open Source Tool Available on GitHub Research-Oriented Tool New models, optimizations, scheduling Eclipse-based Integrated Tool Several plug-ins, metamodels Extended Web Tutorials 23

24 Other Tools INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES OpenMP, OpenEM Adding Rapid Prototyping MAPS Compiler, Polycore Polymapper, SynDEx Open-source code 24

25 PREESM Features INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES 25

26 Some Results on Stereo Matching Theoretical speedup Measured Performance allocated memory lower memory bund Number of cores Number of cores 26

27 Conclusion INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Reduce Software Productivity Gap Design space exploration Rapid Prototyping Extract coarse grain parallelism Portable performance PREESM Dataflow modelling can help! Good decisions necessitate extensive information on both computation and data flow 27

28 Thanks! M. Pelcat, K. Desnos, J. Heulot, C. Guy, J.-F. Nezan, S. Aridhi, "PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP Programming" EDERC, PREESM Tutorial 16:00 17:00 - Room: Oro Plenaria M. Pelcat, S. Aridhi, J. Piat, J.-F. Nezan, "Physical Layer Multicore Prototyping: A Dataflow-Based Approach for LTE enodeb". Springer,