On mapping to multi/manycores

Transcription

1 On mapping to multi/manycores Jeronimo Castrillon Chair for Compiler Construction (CCC) TU Dresden, Germany MULTIPROG HiPEAC Conference Stockholm,

2 Mapping for dataflow programming models MEM subsystem DMAs, semaphores PMU L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA Dataflow: Successful abstraction across different domains Embedded Resource and real-time constraints, heterogeneous platforms Traditionally static models (reduce run-time overhead), but Dynamic models needed: reuire profiling information 2 Prof. J. Castrillon. HiPEAC, 2017

3 Mapping processes/actors & channels (well studied) Trace-based: Analyze unrolled executions to compute compile-time mappings... Use meta-heuristics (popular: genetic algorithms) Need for Better architecture models (standardization?) Convergence of dataflow models (common IR?) Compiler run-time interaction [Castrill13, Castrill14] [Erbas06, Thiele07] 3 Prof. J. Castrillon. HiPEAC, 2017

4 From dataflow to data life-time MEM subsystem DMAs, semaphores PMU L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA Buffer life-times Large applications with multiple constraints (e.g., communication standard) Memory re-used extremely important ILP formulation for temporal mapping of logical buffers to memories under bandwidth and memory size constraints Benchmark: 1ms LTE execution (1000 logical buffers) onto an 80-core machine [Goens16] 4 Prof. J. Castrillon. HiPEAC, 2017

5 Mapping data to data structures Changing graphs (e.g., in social networks) With some changes, better data-representations become more efficient Profiling and monitoring 5 [Schiller16] Prof. J. Castrillon. HiPEAC, 2017

6 Mapping data to data structures Changing graphs (e.g., in social networks) With some changes, better data-representations become more efficient Profiling and monitoring 6 [Schiller16] Prof. J. Castrillon. HiPEAC, x speedup (averaged over seven different graph metrics, Molecular dynamics benchmark)

7 More mapping to come HAEC project: wireless and optical system interconnect Map/configure communication architecture [Fettweis12] Cfaed Orchestration project on [Voelp16] post-cmos technologies Mapping data to heterogeneous memories (reliability, retention, ) Map computation to truly heterogeneous resources 7 Prof. J. Castrillon. HiPEAC, 2017

8 Summary Described several mapping problem formulations Dataflow to heterogeneous multi-cores Buffer lifetimes to interconnect and memories Data to data structures Outlook: Interesting mapping problems coming up (e.g., in HAEC and cfaed) 8 Prof. J. Castrillon. HiPEAC, 2017

9 References [Castrill14] J. Castrillon and R. Leupers, Programming Heterogeneous MPSoCs: Tool Flows to Close the Software Productivity Gap. Springer, 2014 [Castrill13] J. Castrillon, R. Leupers, and G. Ascheid, MAPS: Mapping concurrent dataflow applications to heterogeneous MPSoCs, IEEE Transactions on Industrial Informatics, vol. 9, no. 1, pp , 2013 [Erbas06] Erbas, C., et al Multiobjective Optimization and Evolutionary Algorithms for the Application Mapping Problem in Multiprocessor System-on-Chip Design, IEEE Transactions on Evolutionary Computation, 2006, 10, [Fettweis12] Fettweis, G.; Nagel, W. & Lehner, W. Pathways to servers of the future: highly adaptive energy efficient computing (HAEC), Proceedings of the Conference on Design, Automation and Test in Europe, 2012, [Goens16] Goens, A., et al. An Optimal Allocation of Memory Buffers for Complex Multicore Platforms, Journal of Systems Architecture, Elsevier, 2016, 66-67, [Schiller16] Schiller, B., et al. Compile- and Run-time Approaches for the Selection of Efficient Data Structures for Dynamic Graph Analysis, Journal of Applied Network Science, 2016, 1, 1-22 [Thiele07] Thiele, L.; et al., Mapping Applications to Tiled Multiprocessor Embedded Systems, Proceedings of the Seventh International Conference on Application of Concurrency to System Design, IEEE Computer Society, 2007, [Voelp16] Voelp, M., et al., The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware. Proceedings of the 1st International Workshop on Post-Moore's Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Prof. J. Castrillon. HiPEAC, 2017