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1 High-Speed Interface Driven PCB Design (Net Group, Aixx, Floorplanning etc) Mika Ho / Graser 31/Oct/2014
2 Topic Chapter One An Interface Example DDRx An Example: Timing Relationship for DDR3 Case Description Routing condition Using features Before Interactive Routing You must define well You might need to define well
3 Topic Chapter Two Net Groups CPU[0]_BANK[0] CHNLA_ADDR_CMD CHNLB_ADDR_CMD CHNLA_CLOCKS CHNLB_CLOCKS CHNLA_CTRL CHNLB_CTRL CHNLA_DATA CHNLB_DATA Plan 1 st CLOCKS 2 nd Target Pre-routing 3 rd ADDR CMD & CLTR 4 th DATA Routing Result Conclusion What Else?
4 Topic Chapter Three Routing Flow Optimize Timing vision Auto-interactive Delay Tune (AiDT) Auto-interactive Phase Tune (AiPT) Auto-interactive Add Connect (AiAC) Auto-interactive Convert Corner (AiCC) Auto-interactive Breakout (AiBT) Auto-interactive Trunk Routing (AiTR)
5 Chapter One
6 An Interface Example - DDRx PCB designers need to connect interfaces quickly and easily Today s interfaces cannot be modeled in single-level hierarchy Memory Controller IC byte lane 0 byte lane 1 byte lane 2 byte lane 3 byte lane 4 byte lane 5 byte lane 6 byte lane 7 Memory Devices DATA signals DQ<7..0> byte lane x Strobe signals DQS_P & DQS_N Mask signal DQM
7 Timing closure on advanced highspeed interfaces is iterative, frustrating, and time consuming Market demands products that are faster, have more bandwidth, and use less power Increasing use of standards-based interfaces DDR2 DDR3 DDR4 PCI Express Gen1 Gen2 Gen3 Supply voltage: 1.8V 1.5V 1.2V MEM CTRLR Differential Clock Data Bytelane (5) Differential Clock D I Data Bytelane (5) M M Address / Command / Control Address / Command / Control Differential Clock Data Bytelane (4) V T T VTT VTT D I M M V T T VTT Increasingly sensitive signals Ripples through power supply Crosstalk Complex set of electrical and layout implementation constraints Differential Clock Data Bytelane (4) VTT
8 An Example: Timing Relationship for DDR3 Data ADDR/CMD CONTROL Strobe CLOCKS CLOCKS CLOCKS Complex matching requirements 4 sets of clocks, 8 sets of strobes Match CLKs, strobes, and data AND Match CLKs, ADDR/CMD, and CONTROL Memory Controller CONTROL ADDR/CMD Clocks DATA ODT DRAM TERMINATION
![Case Description Routing Condition : DDR Portion Area: Critical Signal: Net Group: CPU[0]_BANK[0]-CHNLA_ADDR_CMD (24) CPU[0]_BANK[0]-CHNLB_ADDR_CMD (24) CPU[0]_BANK[0]-CHNLA_CLOCKS (8)](/docs-images/87/95587437/images/9-2.jpg "CPU[0]_BANK[0]-CHNLB_CLOCKS (8) CPU[0]_BANK[0]-CHNLA_CTRL (16) CPU[0]_BANK[0]-CHNLB_CTRL (16) CPU[0]_BANK[0]-CHNLA_DATA (90) CPU[0]_BANK[0]-CHNLB_DATA (90) Total: 276 nets Stackup: 12")
9 Case Description Routing Condition : DDR Portion Area: Critical Signal: Net Group: CPU[0]_BANK[0]-CHNLA_ADDR_CMD (24) CPU[0]_BANK[0]-CHNLB_ADDR_CMD (24) CPU[0]_BANK[0]-CHNLA_CLOCKS (8) CPU[0]_BANK[0]-CHNLB_CLOCKS (8) CPU[0]_BANK[0]-CHNLA_CTRL (16) CPU[0]_BANK[0]-CHNLB_CTRL (16) CPU[0]_BANK[0]-CHNLA_DATA (90) CPU[0]_BANK[0]-CHNLB_DATA (90) Total: 276 nets Stackup: 12 layers
10 Case Description Using features Allegro PCB Designer v16.6 s034 Design Planning Option High-Speed Option
11 Before Interactive Routing You must define well Constraints Regions Keep in/out areas Fanout Routing layer You might need to define well Cooper in power plane layers
12 Chapter Two
13 Net Groups (Enhanced by QIR#5) CPU[0]_BANK[0]
14 Net Groups CPU[0]_BANK[0]
15 Net Groups CPU[0]_BANK[0] Hierarchy : Top Level
16 Net Groups CPU[0]_BANK[0] Down Hierarchy
17 Net Groups CPU[0]_BANK[0] Down Hierarchy : Mid Level
18 Net Groups CPU[0]_BANK[0] Hierarchy : Bottom Level
19 Net Groups CPU[0]_BANK[0]-CHNLA_ADDR_CMD
20 Net Groups CPU[0]_BANK[0]-CHNLB_ADDR_CMD
21 Net Groups CPU[0]_BANK[0]-CHNLA_CLOCKS
22 Net Groups CPU[0]_BANK[0]-CHNLB_CLOCKS
23 Net Groups CPU[0]_BANK[0]-CHNLA_CTRL
24 Net Groups CPU[0]_BANK[0]-CHNLB_CTRL
25 Net Groups CPU[0]_BANK[0]-CHNLA_DATA
26 Net Groups CPU[0]_BANK[0]-CHNLB_DATA
27 Net Groups and Placement Quick and easy way to verify your placement The container gives you a way to visualize the overall routing domain of the interface Visual placement checks let you see parts out-of-place The polygon envelops ALL the pins of nets in the net group TERMINATOR IS OUT OF PLACE TERMINATION BELONGS HERE
28 Plan (Design Planning Option) 1 st CLOCKS (Channel A & B)
29 Plan (Design Planning Option) 1 st CLOCKS (Channel A & B) - Timing vision (High-Speed option)
30 Plan (Design Planning Option) 1 st CLOCKS (Channel A & B) - AiPT (High-Speed option)
31 Plan (Design Planning Option) 2 nd Target pre-routing
32 Plan (Design Planning Option) 3 rd ADDR CMD & CTRL (Channel A & B)
33 Plan (Design Planning Option) 3 rd ADDR CMD & CTRL (Channel A & B) - Timing vision (High-Speed option)
34 Plan (Design Planning Option) 3 rd ADDR CMD & CTRL (Channel A & B) - AiDT(High-Speed option)
35 Plan (Design Planning Option) 3 rd ADDR CMD & CTRL (Channel A & B) - AiDT(High-Speed option)
36 Plan (Design Planning Option) 4 th DATA (Channel A & B)
37 Plan (Design Planning Option) 4 th DATA (Channel A & B) - Unplanning
38 Plan (Design Planning Option) 4 th DATA (Channel A & B) - Manual add connection
39 Plan (Design Planning Option) 4 th DATA (Channel A & B) - Timing vision (High-Speed option) - DRC Phase view
40 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiPT(High-Speed option)
41 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiPT(High-Speed option)
42 Plan (Design Planning Option) 4 th DATA (Channel A & B) - Manual Phase Tuning
43 Plan (Design Planning Option) 4 th DATA (Channel A & B) - Timing vision (High-Speed option) - DRC Timing view
44 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig1 layer
45 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig1 layer
46 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig2 layer
47 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig2 layer
48 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig3 layer
49 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig3 layer
50 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig4 layer
51 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig4 layer
52 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig5 layer
53 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig5 layer
54 Plan (Design Planning Option) 4 th DATA (Channel A & B) - Manual fine tuning + AiDT - Sig5 layer
55 Plan (Design Planning Option) 4 th DATA (Channel A & B) - Manual fine tuning + AiDT - Sig5 layer
56 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig6 layer
57 Plan (Design Planning Option) 4 th DATA (Channel A & B) - AiDT (High-Speed option) - Sig6 layer
58 Routing Result Timing view
59 Routing Result Phase view
60 Conclusion DDR (276 Nets) Setting Time: About 30 ~ 120 mins Automation Time : About 40 ~ 60 mins Manual Time: About 2 ~ 6 hrs This case : Took 5 hrs
61 What else
62 Chapter Three
63 Routing Flow Fan out Break out Route Plan Route Optimize
64 Optimize Auto-interactive Delay Tune (AiDT High Speed Option) (Enhanced by QIR#4)
65 Optimize Auto-interactive Phase Tune (AiPT High Speed Option) (Enhanced by QIR#4)
66 Optimize Auto-interactive Add Connect (AiAC PCB Designer) Scribble Mode (Enhanced by QIR#7) Off angle fit Exact fit
67 Optimize Auto-interactive Add Connect (AiAC PCB Designer) Scribble Mode (Enhanced by QIR#7)
68 Optimize Auto-interactive Convert Corner (AiCC PCB Designer)
69 Optimize Auto-interactive Breakout (AiBT Design Planning Option) (Enhanced by QIR#6) For enterprise customers who design PCBs with high-speed interfaces such as DDR3, PCI Express 3.0, SATA, HDMI, USB 3, XAUI, SFP+ Helps you plan breakout of both components tied to an interface Reduce routing steps and improve efficiency Interface breakout (both ends) analysis Canvas-driven inputs for direction, distance, sequence Rat ordering and layering Split Views allows working on both ends of an interface zoomed-in
70 Optimize Auto-interactive Trunk Routing (AiTR Design Planning Option) (Enhanced by QIR#7) New Auto-Interactive function designed to route the trunk or main section of an interface 1 2 Works with Auto-interactive Breakout Tuning Flow the Bundle Run Auto-Interactive Breakout on both ends Trunk Route follows bundle path (approximately) 3 Accelerates time to breakout and route an interface
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