The Control Server: A Computational Model for Real Time Control Tasks

Transcription

1 5th Euromcro Conference on Real Tme Systems, Porto, Portugal, July The Control Server: A Computatonal Model for Real Tme Control Tasks Anton Cervn Department of Automatc Control Lund nsttute of Technology Box 8, SE Lund, Sweden anton@control.lth.se Johan Eker Research Department Ercsson Moble Platforms AB SE Lund, Sweden johan.eker@emp.ercsson.se Abstract The paper presents a computatonal model for realtme control tasks, wth the prmary goal of smplfyng the control and schedulng codesgn problem. The model combnes tme trggered / and nter task communcaton wth dynamc, reservaton based task schedulng. To facltate short nput output latences, a task may be dvded nto several segments. Jtter s reduced by allowng communcaton onlyatthebegnnngandattheendofasegment. Akeypropertyofthemodelsthatbothschedulablty and control performance of a control task wll depend on the reserved utlzaton factor only. Ths enables controllers to be treated as scalable realtme components. The model has been mplemented n a real tme kernel and valdated n a real tme control applcaton.. ntroducton Tradtonal schedulng models gve poor support for codesgn of mult threaded real tme control systems. ne dffculty les n the nonlnearty n schedulng mechansms such as rate monotonc (RM) or earlest deadlne frst (EDF) schedulng: a small change n a task parameter e.g., perod, executon tme, deadlne, or prorty may gve rse to unpredctable results n terms of nput output latency (n short, latency) and jtter. Ths s crucal, snce the performance of a controller depends not only on ts samplngperod,butalsoonthelatencyandthejtter. n the control desgn, t s straght forward to account for a constant latency, whle t s dffcult to address varyng or unknown delays. nthesemnalluandlaylandpaper [Luand Layland, 973], t s assumed that / s performed perodcally by hardware functons, ntroducng a one sample delay n all control loops closed over the computer. Ths scheme does provde a qute nce separaton between schedulng and control desgn. From a schedulng perspectve, the controller can be descrbed by a perodc task wth a perod T, a computaton tme C, and a deadlne D = T. From a control perspectve, the controller wll have a samplngperodoftandaconstantlatencyl =T. Ths allows the control desgn and the real tme desgn to be carred out n relatve solaton. However, the one sample latency degrades the control performance and s ultmately a waste of resources (more on ths later). A common alternatve mplementaton s therefore to perform the / requests wthn the task loop and output the control sgnal as soon as possble n each perod (e.g., [Klen et al., 993; Åström and Wttenmark, 997]). At ths pont, however, the desgn problem becomes very complcated. The / jtter and latency of a controller are now affected by varatons n ts own executon tme as well as nterference from hgher prorty tasks (whch n turn depend on the varatons n the task executon tmes, the phasng of the perodc tasks, the arrval pattern of sporadc tasks, etc.). n the best case, t may be possble to derve formulas for the worst case and bestcase response tmes of the tasks (e.g., [Audsley et al., 993; Redell and Sanfrdson, 2002]), but ths nformaton s stll not suffcent to accurately predct the performance of the controllers. Furthermore, as argued n [Jeffay and Goddard, 200], wth standard RMandEDFschedulngtcanbedffculttomap task mportance nto prortes and/or deadlnes. These algorthms also perform poorly f tasks devate fromtherassumedbehavororfthecpushould become overloaded.. Model vervew The computatonal model we propose combnes elements from the synchronzed / model of Gotto [Henznger et al., 200] wth the CPU resource reservaton model of the constant bandwdth server (CBS) [Aben and Buttazzo, 998]. The prmary goal of the model s to facltate smple codesgn of flexble realtme control systems. n partcular, the model should provde (R) solaton between unrelated tasks, (R2) short nput output latences,

2 (R3) mnmal samplng jtter and nput output jtter, (R4) a smple nterface between the control desgn and the real tme desgn, (R5) predctable control and real tme behavor, also nthecaseofoverruns,and (R6) the possblty to combne several tasks (components) nto a new task (component) wth predctable control and real tme behavor. Requrement (R)sfulflledbytheuseofconstant bandwdth servers. The servers make each taskappearasftwasrunnngonadedcatedcpu wthagvenfractonoftheorgnalcpuspeed.to facltate short latences (requrement (R2)), a task maybedvdedntoanumberof segments,whch are scheduled ndvdually. A task may only read nputs (from the envronment or from other tasks) at thebegnnngofasegmentandwrteoutputs (tothe envronmentortoothertasks)attheendofasegment. All communcaton s handled by the kernel and s hence not prone to jtter (requrement (R3)). Requrements (R4) (R6) are addressed by the combnaton of bandwdth servers and statcally scheduled communcaton ponts. For perodc tasks wth constant executon tmes, the model creates the lluson of a perfect dvson of the CPU, equvalent to the Generalzed Processor Sharng (GPS) algorthm [Parekh and Gallager, 993]. The model makes t possble to analyze each task n solaton, from both schedulng and control ponts of vew. Lke ordnary EDF, schedulablty of the task set s smply determned by the total CPU utlzaton (gnorng context swtches and the / operatons performed by the kernel). The performance of a controller can alsobevewedasafunctonoftsallotedcpushare. These propertes make the model very sutable for feedback schedulng applcatons. Furthermore, the model makes t possble to combne two or several communcatng tasks nto a new task.thenewtaskwllconsumeafractonofthe CPUequaltothesumoftheutlzatonoftheconsttutng tasks. The new task wll have a predctable / pattern, and, hence, also predctable control performance. Control tasks may thus be treated as realtme components, whch can be combned nto new components. n the end, we beleve that the model wll be a sutable platform for adaptaton to varyng task sets and CPU loads,.e., feedback schedulng. As new control tasks are actvated or old controllers change mode, the computng resources should be redstrbuted to provde optmal control performance fortheoverallsystem.thstopcwllbetreatedn subsequent papers..2 Related Work Gotto [Henznger et al., 200] s an abstract programmng model for the mplementaton of embedded control systems. Smlar to our model, / and communcaton are tme trggered and assumed to take zero tme, whle the computatons nbetween are assumed to be scheduled n real tme. A serous drawbackwththemodelsthatamnmumofone sample nput output latency s ntroduced n all control loops. Also, Gotto does not address the schedulng problem. Wthn the Ptolemy project, a computatonal doman called Tmed Multtaskng (TM) has been developed [LuandLee,2003].nthemodel,tasks (or actors n the termnology of Ptolemy) may be trggered by both perodc and aperodc events. nputs arereadwhenthetaskstrggeredandoutputsare wrtten at the specfed task deadlne. The computatons nbetween are assumed to be scheduled by a fxed prorty dspatcher. n the case of a deadlne overrun, an overrun handler may be called. Agan, the schedulng problem s not explctly addressed by the model. The Constant Bandwdth Server [Aben and Buttazzo, 998] was orgnally proposed as a means to bound the utlzaton of soft real tme tasks wth varyng or unknown computatonal demands. A varant calledcbs hd was ntroduced to schedulecontrol tasks wth varyng executon tmes n [Caccamo etal.,2000b].thedeawastoextendthesamplng perod of the controller by addng small chunks of budgettothetaskntheeventofanoverrun.the problems of / jtter and latency were not consdered, however. The dea of reducng jtter usng dedcated, hghprorty tasks or nterrupts handlers for nput and output operatons has been proposed many tmes before, e.g., [Locke, 992; Klen et al., 993; Cervn, 999; Albertos et al., 2000]..3 utlne Therestofthspapersoutlnedasfollows.nthe next secton, the model s stated n more formal terms. Secton 3 deals wth the control and schedulng codesgn problem. Secton 4 dscusses the possblty of vewng control tasks as real tme components.themodelhasbeenmplementednarealtmekernelandthssreportednsecton5.the results of some experments on a control applcaton aregvennsecton6.fnally,secton7gvesthe conclusons and suggestons for future work. 2. TheModel The Control Server (CS) model assumes preemptve deadlne schedulng of tasks n a unprocessor system. To guarantee solaton, all tasks n the system

3 must belong to ether one of two categores: CS tasks, sutable for control loops and other perodc actvtes wth hgh demands for nput/output tmng accuracy. Tasks served by ordnary CBS servers, ncludng aperodc, soft, and non real tme tasks. 2. CSTasks ACStask τ sdescrbedby acpushareu, aperodt, areleaseoffset φ, a set of n segments S,S2,...,Sn of lengthsl,l2,...,ln suchthat n j= lj =T, a set of nputs (assocated wth physcal nputs or shared varables), and asetofoutputs (assocatedwthphyscal outputs or shared varables). AssocatedwtheachsegmentS j are asubsetofthetasknputs, j, acodefunctonf j,and asubsetofthetaskoutputs, j, Thesegmentscanbethoughtof asastatccyclc schedule for the readng of nputs, the wrtng of outputs,andthereleaseofjobs.atthebegnnngofa segments j,.e.,whent = φ + j k= lk (modt ),the nputs j arereadandajobexecutngf j s released. Attheendofthesegment,.e.,whent= φ + j k= lk (modt ),theoutputs j arewrtten. ThejobsproducedbyaCStask τ areservedona frst come, frst served bass by a dedcated, slghtly modfed CBS wth the followng attrbutes: aserverbandwdthequaltothecpushareu, adynamcdeadlned, aserverbudgetc,and asegmentcounterm. Theserversntalzedwthc =m =0andd = φ. The rules for updatng the server are as follows: Durngtheexecutonofajob,thebudgetc s decreased at unt rate. f,atanytme,c =0,or,fanewjobarrves attmerandd =r,then thecountersupdated,m :=mod(m,n ) +, thedeadlnesmoved,d :=d +l m,and thebudgetsrechargedtoc :=U l m. Segments Job executon CBS budget 2 S S 2 S S 2 f f 2 f f t Fgure ExampleofaCStaskexecutngalone.Theup arrows ndcate job releases and the down arrows ndcate deadlnes.theoverrunatt=7causesthedeadlnetobe postponedtotheendofthenextsegment. The rules are somewhat smplfed compared to the orgnal CBS rules [Aben and Buttazzo, 998] due to the predctable pattern of release tmes and deadlnes. The only real dfference from an ordnary CBSsthatherea dynamcserverperod,equalto thecurrentsegmentlength,l m,sused. Fgure shows an example of a CS task wth two segments executng alone. Ths s a typcal model of a control algorthm, whch has been splt nto two parts: Calculate utput and Update State. The lengths of the segments are 2 and 4 unts respectvely,andthetaskcpushares U = 0.5. At thebegnnngofthefrstsegment,annputs read,andattheendofthefrstsegment,anoutput swrtten.thetwofrstjobsconsumelessthanther budgets (whch are and 2 unts respectvely), whle thethrdjobhasanoverrunattme7.thscauses the deadlne to be moved to the end of the next segmentandthebudgettoberechargedto2unts (hence borrowng budget from the fourth job). n ths example, the latency s constant and equal to 2unts (thelengthofthefrstsegment)desptethe varaton n the job executon tmes. Note that CS rules allow for budget rechargng across the task perod. The server deadlne of a task that has constant overruns wll be postponed repeatedly and eventually approach nfnty. 2.2 Communcaton and Synchronzaton The communcaton between tasks and the envronment requres some amount of bufferng. When an nputsreadatthebegnnngofasegment,thevalue sstorednabuffer.thevaluenthebuffersthen read from user code usng a real tme prmtve. The read operaton s non blockng and non consumng,.e.,avaluewllalwaysbepresentnthebufferand the same value can be read several tmes. Smlarly, another real tme prmtve s used to wrte a new outputvalue.thevaluesstorednabufferands wrttentotheoutputattheendoftherelevantsegment. The wrte operaton s non blockng and any t t

4 old value n the buffer wll be overwrtten. Communcaton between tasks s handled va shared varables. f an nput s assocated wth a shared varable, the value of the varable s coped tothenputbufferatthebegnnngoftherelevant segment. Smlarly, f an output s assocated wth a shared varable, the value n the output buffer scoped tothesharedvarableattheendofthe relevant segment. f two tasks shouldwrte to thesame physcal output or shared varable at the same tme, the actual wrte order s undefned. More mportantly, fonetaskwrtestoasharedvarableandanother taskreadsfromthesamevarableatthesametme, the wrte operaton takes place frst. The offsets can hencebeusedtolneuptaskssuchthattheoutput from one task s mmedately read by another task, mnmzng the end to end latency. The use of buffers and non blockng read and wrte operatons allow tasks wth dfferent perods to communcate. The perods of two communcatng tasks need not be harmonc, even f ths makes most sense n typcal applcatons. However, for the kerneltobeabletoaccuratelydetermnefaread and wrte operaton really occurs smultaneously, theoffsets,perods,andsegmentlengthsofasetof communcatng tasks need to be nteger multples of a common tck sze. For ths purpose, communcatng tasks are gathered nto task groups. Ths s descrbed further n the mplementaton secton. 2.3 Schedulng Propertes Fromaschedulabltypontofvew,aCStaskwth thecpushareu sequvalenttoacbsserverwth thebandwdthu.bypostponngthedeadlnewhen the budget s exhausted, the loadng factor of the jobs servedbythecbscanneverexceedu.thesame argumentholdsforthemodfedcbsusednthecs model.asetofcbsandcstaskssthusschedulable fandonlyf U. () fthesegmentlengthsofacstask τ arechosen such that l j =Cj /U, (2) where C j denotes the worst case executon tme (WCET)ofthecodefunctonf j,overrunswllnever occur (.e., the budget wll never be exhausted before theendof thesegment),andalllatenceswllbe constant. For tasks wth large varaton n ther executon tme, t can sometmes be advantageous to assgn segment lengths that are shorter than those gvenbyeq. (2).Thsmeansthatsomedeadlnes wllbepostponedandthatthetaskmaynotalways produce a new output n tme, delayng the output oneormoreperods.anexampleofwhenthscan actually gve better control performance (for a gven valueofu )sgvenlater. 3. Control and Schedulng Codesgn The control and schedulng codesgn problem can benformallystatedasfollows:gvenasetofprocesses to be controlled and a computer wth lmted resources, desgn a set of controllers and schedule them as real tme tasks such that the overall control performance s optmzed. Wth dynamc schedulng algorthms such as EDF and RM, the general desgn problem s extremely dffcult due to the complex nteracton between task parameters, control parameters, schedulablty, and control performance. Wth our model, the lnk between the schedulng desgnandthecontroldesgnsthecpushareu. Schedulablty of a task set s smply determned by the total CPU utlzaton. The performance (or cost) J of a controller executng n a real tme system can roughly speakng be expressed as a functon of the samplng perod T, the nput output latency L,andthejtterj: J =J(T,L,j). (3) Assumng that the frst segment contans the Calculate utput part of the control algorthm, and that the segment lengths are chosen accordng to Eq. (2), executon under the Control Server mples T = l k = C k /U, L =l =C /U, j =0. (4) The only ndependent varable n the expressons above s U. The control performance can thus be expressedasafunctonofuonly: J =J(U). (5) Assumng a lnear controller, a lnear plant, and a quadratc cost functon, the performance of the controller for dfferent values of U can easly be computed usng, e.g., the Jtterbug toolbox [Lncoln and Cervn, 2002]. The elmnaton of the jtter has several advantages. Frst,t s easy to desgn a controller that compensates for a constant delay. Second, the performance degradaton assocated wth the jtter s removed. Thrd, t becomes possble to accurately predct the performance of the controller. The dsadvantage of elmnatng the jtter s that the latency may ncrease, and latency also has a negatve mpact on the control performance. ur model, however, allows a control algorthm to be splt ntosegments,andthscanbeusedtoreducethe latency. The mportance of ths feature s llustrated n the frst example below.

5 3. Example : mportance of Reducng Latency Consder optmal control of the ntegrator process dx(t) dt =u(t) +v c (t). (6) Here,xsthestate (whchshouldbecontrolledto zero),usthecontrolsgnal,andv c sacontnuoustme whte nose dsturbance wth zero mean and unt varance. A dscrete tme controller s desgned to mnmze the contnuous tme cost functon J =lm t t t 0 x 2 (s)ds. (7) Dvdng the control computatons nto two segments and choosng the segment lengths n proporton to WCET of theparts, thecontrol server model wll generate equdstant samplng wth the nterval T andaconstantlatencyl.thecostfortheoptmal, delay compensatng controller can be shown to be J(T,L) = T +L( 0.79T +L). (8) 6 (For detals, see [Cervn, 2003].) t can be noted that, nthscase,thecostgrowslnearlywthboththe samplng nterval and the latency. Furthermore, for afxedvalueof J (.e.,aspecfedlevelofperformance), T s determned by L. Ths mples that acontrollerwthashortlatencywllbelesscpudemandng than a controller wth a long latency. n Table, the relatve CPU demand of the ntegrator controller has been computed for dfferent values of therelatvelatencyl/t.thecasel/t =corresponds to a Lu and Layland mplementaton wth aonesampledelay.asthelatencysreduced (by, e.g., a sutable dvson of the control algorthm nto a Calculate utput segment and an Update State segment), the CPU demand of the controller can be decreased. Table Relatve CPU demand of the ntegrator controller for dfferent relatve latences (assumng a fxed level of control performance). L/T CPU demand Example 2: ptmal Perod Selecton n ths example we study the problem of optmal perod selecton for a set of control loops. Ths type of codesgn problem frst appeared n [Seto et al., 996]. n that paper, however, the schedulngnduced latency and jtter was gnored. Suppose for nstance that we want to control three dentcal ntegrator processes (6). The assumed desgngoalstoselectsamplngperodst,t 2,T 3 suchthataweghtedsumofthecostfunctons,e.g., J tot =J(T,L ) +2J(T 2,L 2 ) +3J(T 3,L 3 ), (9) s mnmzed subject to the utlzaton constrant U = C T + C T 2 + C T 3. (0) Here, C s the (constant) executon tme of the control algorthm. Dvdng the algorthm nto two segments, our model wll mply the same relatve latencya=l /T forallcontrollers.usng (8)the objectve functon (9) can be wrtten ( J tot = 6 ) +a (T +2T 2 +3T 3 ), () and the soluton to the optmzaton problem s T =b, T 2 =b/ 2, T 3 =b/ 3 (2) whereb =C( ). (Formoregeneralproblems numercal optmzaton must be performed.) Contraryto [Setoetal.,996] (wherermoredf schedulng s assumed), our model allows for the latency and the (non exstent) jtter to be accounted for n the optmzaton. 3.3 Example 3: Allowng verruns For controllers wth large varatons n ther executon tme, t can sometmes be pessmstc to select task perods (and segment lengths) accordng to thewcets.thentutonsthat,gvenataskcpu share,tmaybebettertosampleoftenandoccasonallymssanoutput,thantosampleseldomandalways produce an output. Wth our model, t becomes easy to predct the worst case effects (.e., assumng thattherestofthecpusfullyutlzed)ofsuchtask overruns. Agan consder the ntegrator controller. For smplcty, t s assumed that the controller s mplementedasasnglesegment,.e.,wehavel=tf no overrun occurs, and that the assgned CPU share su =.Nowassumethattheexecutontmeofthe controller s gven by the probablty densty functon nfgure2.choosngaperodlessthanthewcet meansthatsomeoutputswll bemssedandthat the actual latency wll vary randomly between T, 2T,3T,etc.,accordngtoaMarkovchan.Theresultng control performance for such a model can be computed usng the Jtterbug toolbox [Lncoln and

6 Probablty Densty Executon Tme Fgure 2 Assumed executon tme probablty densty functon of the ntegrator controller. Cost J Task perod T Fgure3 Costasafunctonofthetaskperodforthe ntegrator controller wth varyng executon tme. Cervn,2002].nFgure3thecost (7)hasbeencomputedfordfferentvaluesofthetaskperod.Theoptmalcost J =.67sobtanedforT =0.76.For thatperod,overrunswlloccurn9%oftheperods (ntroducng a latency of 2T or more). The example showsthatourmodelcanbeusedto cutthetal off executon tme dstrbutons wth safe and predctable results. 4. CS Tasks as Real Tme Components As argued n the prevous secton, gven a control algorthm wth known executon tme C (dvded nto one or several segments), the samplng perod T, the latency L, and the control performance J canbeexpressedasfunctonsofthecpushareu. The predctable control and schedulng propertes allowsacstasktobevewedasascalablereal tme component. Consder for nstance the PD (proportonalntegral dervatve) controller component n Fgure 4. The controller has two nputs: the reference valuerandthemeasurementsgnaly,andoneoutput:thecontrolsgnalu.theuknobdetermnesthe CPU share. An ordnary software component would only specfy the functonal behavor,.e., the PD algorthm. The specfcaton for our real tme component ncludes the resource usage and the tmely behavor and could for nstance look lke ths: Algorthm:u=K (r y) +... Parameters:U,K,... C =ms (onagvenprocessor) T =C/U L =T/4 J =J(U) (gvenasfunctonordagram) Also remember that our model guarantees that the controller wll have the specfed behavor, regardless ofothertasksnthesystem. Next, consder the composton of two PD controllers n a cascaded controller structure, see Fgure5.nthsverycommonstructure,thennercontroller s responsble for controllng the (typcally) fastprocessdynamcsg 2,whletheoutercontroller handles theslower dynamcs G. A cascadedcontroller component can be bult from two PD componentsasshownnfgure6.nthscase,tsassumed that the nner controller should have twce the samplng frequency of the outer controller (reflectng the speed of the processes). Ths s acheved byassgnngthesharesu/3topdand2u/3to PD2,UbengtheCPUshareofthecompostecontroller. The end to end latency n the controller can be mnmzed by a sutable segment layout, see Fgure7. The schedulablty and performance of the cascaded controller wll, agan, only depend on the totalassgnedcpushareu.thecontrollerwllhave a predctable nput output pattern, and ts performance can be computed usng the Jtterbug toolbox [Lncoln and Cervn, 2002; Cervn, 2003]. Note that such composton s not possble wth ordnary threads,.e., two communcatng threads cannot be treated as one, nether from schedulablty nor control perspectves. 5. mplementaton ThetaskmodelhasbeenmplementedntheSTRK real tme kernel [Andersson and Blomdell, 99], developed at the Department of Automatc Control, Lund nsttute of Technology. The orgnal kernel s a standard prorty preemptve real tme kernel wrtten n Modula 2, runnng on multple platforms. r y U PD Fgure 4 A PD controller component. The U knob determnes both the schedulablty and the control performance. u

7 Computer Process Ctrl Ctrl2 G 2 G Tmer expry: Tme handler: (*)(vod) EDFTask release: Tme deadlne: Tme process: (*)(vod)..* r y y 2 Fgure 5 Cascaded controller structure. r y U/3 PD u U m CascPD r y 2U/3 PD2 Fgure 6 A cascaded PD controller component. For ths project, the Motorola PowerPC was chosen becauseoftshghclockresoluton (40nsona00 MHz processor). ThekernelwasmodfedtouseEDFasthebasc schedulng polcy, and hgh resoluton tmers (hardware clock nterrupts that trgger user defned handlers) were ntroduced. A number of data structures for CBS servers, CS tasks, segments, nputs, and outputs, etc., were ntroduced, see Fgure 8. For synchronzaton reasons, communcatng CS tasks must shareacommontmebaseandaregatheredntask groups. 5. Task Group Tmng Eachtaskgroupusesatmertotrggerthereadng of nputs, wrtng of outputs, and release of segments oftaskswthnthegroup.thestructureofthetask group tmer nterrupt handler s shown n Lstng. The average executon tme of the handler was about 5 µs n the mplementaton. AssocatedwtheachCStasksasemaphorethat susedtohandlethereleaseofthesegmentjobs. nternally, every CS task s mplemented as a smple loop, see Lstng 2. τ τ 2 0 S S 2 S S 2 φ 2 S2 S2 2 S2 S2 2 S2 S2 2 S2 Fgure 7 Segment layout n the cascaded PD controller.task τ 2 sgvenaphase φ 2 = l suchthatthe valuewrttenbys smmedatelyreadbys 2. u u TaskGroup tcksze: Duraton SharedVarn data: vod* sze: nt CSTask..* offset: nt codefcn: (*)(nt, vod*) currentsegment: nt Analogut channel: nt value: double 0.. CBS bandwdth: double deadlne: Tme budget: Duraton perod: Duraton..* 0..* 0..* Segment nput utput length: nt nputs: nt[] outputs: nt[] Analogn channel: nt value: double SharedVarut data: vod* sze: nt Fgure 8 The varous data structures n the mplementaton. Lstng Pseudocode of task group tmng. for (each task n the task group) { f (current segment s fnshed) { Wrte outputs (f any); ncrease segment counter; } } for (each task n the task group) { f (new segment should begn) { Read nputs (f any); Release segment job (sgnal semaphore); } } Determne next wakeup tme; Set up tmer; 5.2 AP The kernel provdes a number of prmtves for defnng task groups, EDF tasks, CS tasks, etc. The codeofacstaskswrttenaccordngtoaspecal format llustrated wth a PD controller n Lstng 3. The kernel prmtves Readnput and Wrteutput are used to access the nputs and outputs assocated wth the segment. Lstng 2 nternal mplementaton of CS task. whle (true) { ncrease segment counter; Wat on semaphore; Call codefcn(segment,data); }

8 Lstng 3 PD controller wrtten n Modula 2. PRCEDURE PDTask(segment: CARDNAL; data: PDData); VAR r, y, u: LNGREAL; BEGN CASE segment F : r := Readnput(); y := Readnput(2); u := PD.Calculateutput(data, r, y); Wrteutput(, u); 2: PD.UpdateState(data); END; END PDTask; (a) (b) Poston Dst Ctrl Tme Tme Fgure 0 Control experment under EDF schedulng: (a) control performance, and (b) close up of executon traceatt =20. (a) Poston Tme Fgure 9 The ball and beam process. (b) Dst 6. Control Experments Some control experments were performed on the ball and beam process, see Fgure 9. The objectve stomovetheballtoagvenpostononthebeam. Thenputtotheprocesssthebeammotorvoltage, and the outputs are voltages representng the beam angle and the ball poston. The process s regulated wth a cascaded PD controller, mplemented as a sngle task (n order to keep the example smple). The controller s desgned wth the samplng nterval T =40msandhastheexecutontmeC =20ms, thusconsumngu =0.5oftheCPU. (Togenerate ahghcpuload,busycycleswerensertednthe task code). The code s dvded nto two segments: Calculate utput (5 ms) and Update State (5 ms). Alsoexecutngnthesystemsasporadctask wth amnmumnterarrvaltmeof T 2 = 20ms andanassumedwcetofc 2 =0ms.Betweentme 0 and 20, the actual executon tme vares randomly between5and0ms.attmet=20,thedsturbance task starts to msbehave and has an executon tme thatvaresrandomlybetween5and50ms. The behavor of the real tme control system under ordnary EDF schedulng and under CS schedulng was compared n dfferent experments. n each experment, the executon trace (.e, the task schedule) was logged, together wth the measurements from the process. Ctrl Tme Fgure Control experment under CS schedulng: (a) control performance, and (b) close up of executon trace att =20. The result of a control experment under EDF schedulng s shown n Fgure 0. The performance ssatsfactoryuptot =20,whenthesporadctask starts to consume a large part of the CPU tme, whch dsturbs the control task. n a second experment, runnng the tasks under CS schedulng, both tasks were assgned a CPU share of 50%. The expermental results are shown n Fgure. The controller executon s no longer dsturbed by the msbehavng sporadc task, and (not vsble n the trace) there s no longer any / jtter. The control performance s dentcal both before and aftertmet = Concluson We have presented the Control Server, sutable for the mplementaton of control tasks n flexble realtme systems. Features of the model nclude small latency and jtter, and solaton between unrelated

9 tasks. The present work may be extended n several drectons. The CBS servers used could be modfed to use a slack stealng algorthm such as CASH [Caccamo et al., 2000a] or GRUB [Lpar and Baruah, 2000]. Ths could mprove the performance further when the system s under utlzed. We do not account for the nterrupt tme (ncludng the / operaton) n the schedulng analyss. Possbltes for more detaled analyss are found n [Lu and Layland, 973] ( mxed schedulng ) and n [Jeffay and Stone, 993]. Another topc that needs further nvestgaton s the overrun handlng. How should a controller be desgned n order to cope wth postponed outputs? Should segments sometmes be aborted? Also, we would lke to explot the codesgn propertes of the model n feedback schedulng applcatons where the goal s to dynamcally dstrbute the avalable computng resources such that the overall control performance s optmzed. n our prevous work [Cervnetal.,2002]weddnotaccountforthelatency and the jtter n the on lne optmzaton. References Aben, L. and G. Buttazzo (998): ntegratng multmeda applcatons n hard real tme systems. n Proc. 9th EEE Real Tme Systems Symposum. Madrd, Span. Albertos, P., A. Crespo,. Rpoll, M. Vallés, and P. Balbastre (2000): RT control schedulng to reduce control performance degradng. n Proc. 39th EEE Conference on Decson and Control. Sydney, Australa. Andersson, L. and A. Blomdell (99): A real tme programmng envronment and a real tme kernel. n Asplund, Ed., Natonal Swedsh Symposum on Real Tme Systems, Techncal Report No Dept. of Computer Systems, Uppsala Unversty, Uppsala, Sweden. Åström, K. J. and B. Wttenmark (997): Computer Controlled Systems. Prentce Hall. Audsley, N., K. Tndell, and A. Burns (993): The end of the lne for statc cyclc schedulng. n Proc. 5th Euromcro Workshop on Real Tme Systems. Caccamo, M., G. Buttazzo, and L. Sha (2000a): Capacty sharng for overrun control. n Proc. EEE Real Tme Systems Symposum. rlando, Florda. Caccamo, M., G. Buttazzo, and L. Sha (2000b): Elastc feedback control. n Proc. 2th Euromcro Conference on Real Tme Systems, pp Stockholm, Sweden. Cervn, A. (999): mproved schedulng of control tasks. n Proceedngs of the th Euromcro Conference on Real Tme Systems, pp York, UK. Cervn, A. (2003): ntegrated Control and Real Tme Schedulng. PhD thess SRN LUTFD2/TFRT 065 SE, Department of Automatc Control, Lund nsttute of Technology, Sweden. Cervn, A., J. Eker, B. Bernhardsson, and K. E. Årzén (2002): Feedback feedforward schedulng of control tasks. Real Tme Systems, 23:. Henznger, T. A., B. Horowtz, and C. M. Krsch (200): Gotto: A tme trggered language for embedded programmng. n Proc. Frst nternatonal Workshop on Embedded Software. Jeffay, K. and S. Goddard (200): Rate based resource allocaton models for embedded systems. n Proc. Frst nternatonal Workshop on Embedded Software. Jeffay, K. and D. L. Stone (993): Accountng for nterrupt handlng costs n dynamc prorty systems. n Proc. 4th EEE Real Tme Systems Symposum. Klen, M. H., T. Ralya, B. Pollak, R. benza, and M. Gonzalez Härbour (993): A Practtoner s Handbook for Real Tme Analyss: Gude to Rate Monotonc Analyss for Real Tme Systems. Kluwer Academc Publsher. Lncoln, B. and A. Cervn (2002): Jtterbug: A tool for analyss of real tme control performance. n Proceedngs of the 4st EEE Conference on Decson and Control. Las Vegas, NV. Lpar, G. and S. Baruah (2000): Greedy reclamaton of unused bandwdth n constant bandwdth servers. n Proc. Euromcro Conference on Real Tme Systems. Stockholm, Sweden. Lu, C. L. andj. W.Layland (973): Schedulng algorthms for multprogrammng n a hard realtme envronment. Journal of the ACM, 20:, pp Lu, J. and E. Lee (2003): Tmed multtaskng for real tme embedded software. EEE Control Systems Magazne, 23:. Locke, C. D. (992): Software archtecture for hard real tme applcatons: Cyclc vs. fxed prorty executves. Real Tme Systems, 4, pp Parekh, A. and R. Gallager (993): A generalzed processor sharng approach to flow control n ntegrated servces networks: the sngle node case. EEE/ACM Transactons on Networkng, :3, pp

10 Redell,. and M. Sanfrdson (2002): Exact bestcase response tme analyss of fxed prorty scheduled tasks. n Proc. 4th Euromcro Conference on Real Tme Systems. Venna, Austra. Seto, D., J. P. Lehoczky, L. Sha, and K. G. Shn (996): n task schedulablty n real tme control systems. n Proc. 7th EEE Real Tme Systems Symposum, pp Washngton, DC.