FPGA system development What you need to think about. Frédéric Leens, CEO
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1 FPGA system development What you need to think about Frédéric Leens, CEO
2 About Byte Paradigm 2005 : Founded by 3 ASIC-SoC-FPGA engineers as a Design Center for high-end FPGA and board design : GP Series PC Instruments for Test & Debug 2011 : Decision to capitalise on experience of FPGA + T&M Dec. 2014: Creation of Exostiv Labs a separate trade name of Byte Paradigm Focus: FPGA Debug & Verification
3 Byte Paradigm Design Services > 50 year (cumulated) experience in FPGA-based system design
4 ASIC vs FPGA 4 clichés 1. FPGA is a fall-back choice until I can pay ASIC s NRE. 2. FPGA is way too expensive. Where is my 3.00 FPGA? 3. FPGA is just a programmable ASIC. 4. FPGA is less powerful than an ASIC.
5 You know the usual story about ASIC... Source: Altera Source: Broadcom Source: Broadcom Source: Xilinx
6 FPGA design: What does it really cost? 8 engineers, 18 month Extended tool set More IP High-end board 960 k 2 engineers, 6 month Reduced tool set Free or no IP Low-cost board 4 engineers, 12 month Average tool set Some IP Avg board 340 k 96 k
7 Typical FPGA prices per unit 7 (~25 k gates 200 MHz+ 200 kb memory ~100 I/Os) to 1,400 (~2.5 M gates 500 MHz+ 21 Mb memory ~400 I/Os) Prices for 1 unit as seen on Digi-Key for: Spartan-6 XC6SLX4-2TQG144C and Kintex-7 Ultrascale XCKU040-2FFVA1156E
8 Some extreme figures... 25,000 (~10 M gates 500 MHz+ 47 Mb memory 1200 I/Os) Price for 1 unit as seen on Digi-Key for: XC7V2000T-G2FLG1925E-ND
9 FPGA: Beyond NRE... FPGA weigh in the BOM Engineering cost for maintenance / corrections IP fees per unit Cost of software Fast turn around Fast time-to-market Easy path to upgrades Potentially longer product life
10 Choosing the right FPGA
11 Choosing the right FPGA (2)
12 Choosing the right FPGA (3)
13 FPGA selection 2 very different cases DSP-like processor DSP primary usage 128 I/Os 50K ASIC gates 250 MHz clock SoC 1 GHz USB 3.x 100G Ethernet 500K ASIC gates 500 I/Os Large SW content
14 FPGA selection SoC Xilinx Zynq Ultrascale + ZU11EG ZU17EG ZU19EG Quad ARM Cortex-A GHz CPU USB to G Ethernet ~3M to 6M ASIC gates 416 to 572 I/Os Availability: 2016 for early access. No information on prices yet. SoC Multi-CPU 1 GHz CPU USB 3.x 100G Ethernet 500K ASIC gates 500 I/Os Large SW content
15 FPGA selection SoC Candidates: Xilinx Zynq Ultrascale + ZU11EG (~3M) ZU17EG (~6M) ZU19EG (~9M) (Avail. : 2016) Altera Stratix 10 SoC is a potential alternative.
16 FPGA selection DSP Altera Cyclone V 5CEA2 to 5CEA9 50 to x18 mult. 25 to 342 var. precision DSP F256 package with 128 I/O 150 k to 1.8 M gates 250 MHz on 27x27 mult with speed grade C6 (fast). (-C8 speed grade 9x9 mult at 260 MHz) DSP DSP primary usage 128 I/Os 50K ASIC gates 250 MHz clock Price: from 22 for 1 unit
17 Which FPGA vendor?! FPGA Vendors make choices for you! 1. Are the right IP available? 2. Does your team have prior experience with vendor V? 3. Benchmark if you want to, but *before* you have to choose 4. Try P&R on partial design with critical path early in the design cycle and check the impact on: Speed grade, package FPGA family and/or vendor 5. Equivalent gate should be used with care!
18 ASIC vs FPGA : the flow is different......but it is really up to you.
19 FPGA design flow variations - example
20 Why debug & verification is a hot topic Typical FPGA design project 72%* recognize the need to improve debug & verification * of the respondents to our survey
21 A word on Agile development process (1) Values : Individuals and interactions over processes and tools. Working software over comprehensive documentation. Customer collaboration over contract negotiation. Responding to change above following a plan. Consequences: Changing requirements Evolving products Adaptation to changing circumstances,... Impact on flow: from Waterfall to Agile Agile in the real life: Apps : we buy a now and a future Smartphone regular updates
22 FPGA rules for Agile The system must be... 1) Programmable and 2) Field-upgradeable: Configuration management with fallback Software access & hardware access Remote field-upgradeable? Keep upgradeability in mind: 3)! OVER-BUY FPGA!
23 10 steps to choose the right FPGA 1. I/Os Interfaces: define the numbers and types. Model your system as INPUT and OUTPUT flows. 2. Check your need for hard macros (IP)? Need for analog? 3. Check the available IPs. Which ones are free? 4. Price (consider total price over lifetime) 5. Consider multi-chip (or multi-fpga) alternatives Can be *very* cost-effective 6. Over-buy FPGA for prototype. Think to compatible packages Beware of implementation rules and take a margin. Be sceptical about the data sheet and go early to P&R. 7. Define the verification & debug strategy & check tools availability 8. Flow familiarity can let you save a lot since the cost of engineering is dominant 9.! Check chip REAL availability! 10. Rework your algorithm if no FPGA has sufficient resources for your needs.
24 Thank you.
25 Additional slides
26 ASIC vs FPGA : Know your skills 1. ASIC & FPGA flows are different and require different skills Not only HDL or System level Some advanced tools like assertion-based verification are commonplace for ASIC, but not for FPGA. ASIC back-end is a specialty The FPGA flow used to be a subset of the ASIC flow. Things are changing. The ability to (re)-program FPGA leads to conducting some verification steps in the lab. Like it or not, but you ll have to leave the comfort of your workstation. 2. FPGA is not so FPGA anymore Evolution towards system-level languages and methodologies New languages are getting in the pictures: HLS, Catapult, OpenCL FPGA covers very different product realities: from traditional FPGA to very complex system-on-chip
27 FPGA design: What does it really cost? FPGA 'NRE' ( ) Low cost Average High end Length Crew Salaries 57,600 57, , ,200 Software licenses 11,133 31, ,398 Vivado / Quartus: low 1,917 1,917 7,667 Vivado / Quartus / high 3,709 29,670 Simulator 2,816 2,816 11,264 22,528 Other software 6,400 6,400 12,800 51,200 IP licensing 64, ,000 64,000 Standard test board 1,085 2,557 14,390 Kintex-7 eval kit 1,085 1 K7 Avnet DSP kit 2,557 1 Virtex-7 eval kit 2,237 1 Virtex-7 ultrascale eval kit 4,477 1 Virtex-7 characterization kit 7,677 1 Target board 15,000 20,000 40,000 Low end 9,600 1 Mid range, incl. Layout and components 12,800 1 High end 25,600 1 Lab equipment 19,200 4,800 9,600 19,200 First Series 6,400 6,400 12,800 25,600 TOTAL 96, , ,789
28 Byte Paradigm PC-based T&M instruments
29 FPGA Debug & Verification: Exostiv Labs Experience in FPGA Design Test & Measurement Tools FPGA Debug Reloaded
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