FPGA Reconfiguration!
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1 Advanced Topics on Heterogeneous System Architectures Reconfiguration! Politecnico di Milano! Seminar Room, Bld 20! 4 December, 2017! Antonio R. Miele! Marco D. Santambrogio! Politecnico di Milano!
2 Reconfiguration in everyday life! 2
3 3 Reconfiguration in everyday life! Soccer (Par%al Sta%c)
4 4 Reconfiguration in everyday life! Football (Complete Sta%c) Soccer (Par%al Sta%c)
5 5 Reconfiguration in everyday life! Football (Complete Sta%c) Soccer (Par%al Sta%c) yamic) e k c o H Dyn l a % r a (P
6 SoC Reconfiguration! 6
7 SoC Reconfiguration! 7
8 SoC Reconfiguration! 8
9 SoC Reconfiguration! 9
10 SoC Reconfiguration! 10
11 "MANAGER" 11 SoC Reconfiguration!
12 "MANAGER" 12 SoC Reconfiguration!
13 "MANAGER" 13 SoC Reconfiguration!
14 "MANAGER" 14 SoC Reconfiguration!
15 15 SoC Reconfiguration! "MANAGER"
16 16 SoC Reconfiguration! "MANAGER"
17 17 SoC Reconfiguration! "MANAGER"
18 "MANAGER" 18 SoC Reconfiguration!
19 19 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static!
20 20 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static! SYSTEM BOARD/s CARD HOST (e.g., PC)
21 21 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static! SYSTEM BOARD/s CARD HOST (e.g., PC) WHO
22 22 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static! SYSTEM BOARD/s CARD WHO HOST (e.g., PC)
23 23 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static! SYSTEM BOARD/s CARD HOST (e.g., PC)
24 24 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static! SYSTEM BOARD/s CARD HOST (e.g., PC)
25 25 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static! SYSTEM BOARD/s CARD HOST (e.g., PC)
26 26 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static! SYSTEM BOARD/s CARD HOST (e.g., PC)
27 27 SoMC Reconfiguration Scenario! Embedded VS External! Complete VS Partial! Dynamic VS Static! SYSTEM BOARD/s CARD HOST (e.g., PC)
28 28 SoMC Reconfiguration Scenario! SYSTEM BOARD/s CARD HOST (e.g., PC)
29 29 SoMC Reconfiguration Scenario! SYSTEM BOARD/s CARD HOST (e.g., PC)
30 30
31 31 Some Definitions! Object Code: the executable active physical (either HW or SW) implementation of a given functionality!! Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)!
32 32 Some Definitions! Object Code: the executable active physical (either HW or SW) implementation of a given functionality!! Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)!
33 33 Some Definitions! Object Code: the executable active physical (either HW or SW) implementation of a given functionality!! Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)! IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface)!!
34 34 Some Definitions! Object Code: the executable active physical (either HW or SW) implementation of a given functionality!! Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)! IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface)! Reconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture!
35 35 Some Definitions! Object Code: the executable active physical (either HW or SW) implementation of a given functionality!! Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)! IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface)! Reconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture!! Reconfigurable Region: a portion of the device area used to implement a reconfigurable core!
36 36
37 37 5 W! who controls the reconfiguration!
38 38 5 W! who controls the reconfiguration! where the reconfiguration cotroller is located!
39 39 5 W! who controls the reconfiguration! where the reconfiguration cotroller is located! when the configurations are generated!
40 40 5 W! who controls the reconfiguration! where the reconfiguration cotroller is located! when the configurations are generated! which is the granularity of the reconfiguration!
41 41 5 W! who controls the reconfiguration! where the reconfiguration cotroller is located! when the configurations are generated! which is the granularity of the reconfiguration! in what dimension the reconfiguration operates!
42 42 5 W! who controls the reconfiguration! where the reconfiguration cotroller is located! when the configurations are generated! which is the granularity of the reconfiguration! in what dimension the reconfiguration operates!
43 43 Physical Coordinates! 4-Slice VIIP CLB
44 44 Physical Coordinates! SLICE 4-Slice VIIP CLB
45 45 Physical Coordinates! Y SLICE 4-Slice VIIP CLB X
46 46 Physical Coordinates! Y SLICE 4-Slice VIIP CLB X
47 47 Physical Coordinates! Y SLICE_X67Y Slice VIIP CLB X
48 48 Physical Coordinates! Y SLICE_X67Y75 75 SLICE_X66Y Slice VIIP CLB X
49 49 Switch Box Physical Coordinates! Y SLICE 75 SLICE_X66Y Slice VIIP CLB X
50 50 Reconfigurable Region Definition! The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file! 50
51 51 Reconfigurable Region Definition! The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file! AREA_GROUP "RR1" RANGE = SLICE_X28Y64:SLICE_X41Y127; 51
52 52 Reconfigurable Region Definition! The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file! 52 AREA_GROUP "RR1" RANGE = SLICE_X28Y64:SLICE_X41Y127; AREA_GROUP "RR1" RANGE = RAMB16_X2Y9:RAMB16_X2Y15;
53 RR Area Constraints! 53
54 54 RR Area Constraints! Xilinx S3 Xilinx VIIP
55 55 RR Area Constraints! Xilinx S3 Xilinx VIIP
56 56 RR Area Constraints! Xilinx S3 Xilinx VIIP
57 57 RR Area Constraints! Xilinx V4 Xilinx S3 Xilinx VIIP
58 Advanced Topics on Heterogeneous System Architectures Questions! Reconfiguration! Politecnico di Milano! Seminari Room, Bld 20! 4 December, 2017! Antonio R. Miele! Marco D. Santambrogio! Politecnico di Milano!
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