Metodologie di Progettazione Hardware e Software

Transcription

1 POLITECNICO DI MILANO Metodologie di Progettazione Hardware e Software Reconfigurable Computing - Design Flow - Marco D. Santambrogio marco.santabrogio@polimi.it Outline 2 Retargetable Compiler Basic Idea Description Programming paradigm MOLEN architecture LimboWARE: basic principles VIRGIL YaRA architecture 1

2 Presentation status 3 Retargetable Compiler Basic Idea Description Programming paradigm MOLEN architecture LimboWARE: basic principles VIRGIL YaRA architecture Compiler background Compiler is a quite complex software package Compilers must be particularly reliable Translation of source code into machine independent intermediate representation (IR) Design requires separation into multiple phases Compiler is followed by Assembler, Linker Backend: mapping machine indepent IR to machine dependent asm + machine dependent optimizations 4 2

3 Retargetable Compilers 5 Retargetable Compilers Main Goals Def.: A compileris called retargetable,ifit can be modified to generate asse mbly code for different architectures, while reusing the largest part ofthe co mpiler source code. Adapt to new processors having a single tool for an entire class of target machines Support for design space exploration by editing the target processor model Tradeoff retargetability/code quality: Realistic retargetable compilers focus on a specific class of processor architectures 6 3

4 Retargetable Compilers - degrees Parameterizable: Compiler source code is fixed, retargeting mainly by adjusting several parameters User retargetable: User w/o in-depth compiler knowledge can change the target Developer retargetable: Compiler developer (or very experienced user) can retarget the compiler with limited effort Portable: Some source code can be kept, but a lot of code needs to be newly written 7 Presentation status 8 Retargetable Compiler Basic Idea Description Programming paradigm MOLEN architecture LimboWARE: basic principles VIRGIL YaRA architecture 4

5 Main goals: provide a semi-automatic platform for reconfigurable computing. support the entire design process (rather than isolated parts). targets uni-processor architectures with reconfigurable units (the current version exploit a PPC core processor augmented with an FPGA) These require the development of: programming models (MOLEN) a retargetable compilers for reconfigurable platforms. introduction of hardware software co-design speculations. CAD and design space exploration. 9 Programming Paradigm The ISA is extended with 8 instructions 6 instructions are required for controlling the reconfigurable hardware 2 instructions are required for controlling the reconfigurable hardware This mean that to call a FPGA function the compiler must insert code to: SET the function send input parameters to the FPGA call the EXECUTE on the FPGA move output values back from exchange registers 10 5

6 Code Human Directives Architecture int fact(int n) { if(n<1) return n else return(n*fact(n-1)); } C2C f(.) Retargeted Compiler Binary Code call f(.) HDL SimpleScalar Part III Part II Performance Statistics NO HDL FPGA Part I REVISE 11 The retargetable compiler Generating executable code: Once a function f(.) is identified, the code containing the f(.) logic is eliminated from the source code and replaced by an appropriate FPGA call, together with the appropriate instructions for setting up the FPGA and to start its computation. 12 6

7 MOLEN Architecture CCU: Custom Configured Unit 13 Presentation status 14 Retargetable Compiler Basic Idea Description Programming paradigm MOLEN architecture LimboWARE: basic principles VIRGIL YaRA architecture 7

8 LimboWARE: : The idea The basic idea is to postpone the decision of whether executing a task in HW or in SW moving it at run-time This will be done not for every task, because of code memory overhead, but only where is not possible to take a wise choice at design or compile-time 15 LimboWARE: When - Where Compile-time Unbounded number of execution If n is a number known only at run-time. The limbo choice is wiser than the corresponding one done at compile time (without this information) for(i=0; i<n; i++){ function(); } Execution trace dependent choice between HW and µ- code Functionality already in HW (past) Functionality that in this branch will be used many times (constrained future) 16 8

9 LimboWARE Execution path dependent choice The execution of node 6 depends on the path If the path is the predicate P is TRUE, is executed in HW and the relative µ-code for the SW execution is skipped, by branching after If the path is , the predicate P is FALSE, HW_CALL and JMP are not executed and the µ-code for is executed 17 Presentation status 18 Retargetable Compiler Basic Idea Description Programming paradigm MOLEN architecture LimboWARE: basic principles VIRGIL YaRA architecture 9

10 Provide a workbench VIRGIL: The objectives Integrating and adapting HW/SW codesign methodology to reconfigurable HW scenario Integration of the DRESD reconfigurable HW architecture (YaRA) Introduction of LimboWare mechanisms Development of a retargetable compiler for reconfigurable hardware 19 HW/SW partitioning VIRGIL: Main steps LimboWare code analysis Compile the source code including special LimboWare directives Synthesis and Mapping of the HDL (generated in the first 2 steps) to the Reconfigurable Hardware 20 10

11 VIRGIL: HLR 21 VIRGIL: The Compiler 22 11

12 VIRGIL: The architecture YaRA - FPGA Layers 23 VIRGIL: Needs Development of a retargetable compiler for reconfigurable HW integrating LW functionalities. Integrating and tailoring HW/SW codesign methodologies to reconfigurable hw and LW. Identification of LimboWare and critical function detection WHAT in the code will be translated -> metrics Definition of metrics of source code for SW/LW partitioning and development of the relative tools