System Level Instrumentation using the Nexus specification

Transcription

1 System Level Instrumentation using the Nexus specification Neal Stollon, HDL Dynamics Chairman, IEEE 5001 Nexus Forum HDL Dynamics SoC Solutions

2 System Debug Multicore and SoC Debug is not just a SoC problem anymore Systems integrators see debug as biggest software task Bigger systems, more interactions to monitor, more subtle bugs Remote System debug concurrent data from many chips Standards are more important for support of end applications Automotive, Networking, Aerospace More interest in Debug architectures = Involvement in Nexus

3 Why Nexus 5001 Nexus provides an Instrumentation toolbox for SoC Debug Standard and User defined Debug packet messages Implicit processor agnostic multi-core support Embedded run control, Breakpoints, Triggers, Instruction/data trace Defines recommended IO and register infrastructure ~35 Pre-defined Data Transfer/Trace messages (Tcodes) Ownership Trace Messages - trace the processes, tasks or threads Program Trace Messages - trace of code execution Data Trace Messages trace memory address and values Watchpoint Trace Messages - exact timing when events occur Data Acquisition Trace Messages - control of transmitted data In-Circuit Trace Messages - Provides custom/logic Analyzer trace capabilities User/Vendor defined Tcodes Whatever is required 3

4 Nexus 5001 Debug Environment System Run Control Ctoss Triggering - In/Out System Bus AMBA/OCP Bus Monitor Gasket Inst. Data/Addr trace TCODE & Message Protocol/ Formatting Nexus Registers JTAG Debug Registers AUX /SERDES Out FSMs AUX /SERDES In FSMs JTAG FSMs Auxiliary/ SERDES Output AUX/ SERDES Input JTAG TDI/TDO Applications Logic Performance Trace Debugger, SW Emulation Acquisition, Prototyping Run Time Debugger, Parameter Tuning, Calibration User Defined Domain 5001 Nexus Domain 4 Processor Independent data access Multiple on-chip processor/core support Custom Instruments Packet-Based Messaging Program Trace Data Trace Memory Substitution Vender -Defined 1149 TAP - 2 or 4 wire and/or AUX / SERDES Ports for High Performance Access to resources 4

5 Key Nexus concept Nexus Protocol Optional record event timing (delta) address (Indirect BTM only) Number of instructions since last BTM For multi processor systems to identify active processor Branch Trace Message (BTM) Example Message transfer code Vendor defined Variable length 1 8 bits Vendor defined 6 bits Timestamp U ADDR Instruction Count Message Source TCODE (0x3) Vendor defined Variable length Vendor defined 6 bits Timestamp PAYLOAD Message Source TCODE (0xXX) User Defined Message Example 5

6 What do System Folks want in Debug Real Time Instrumentation Debug and Calibration in the field Nexus - Multiple Trace and Memory and Register Access Methods Nexus - Real Time Read (Trace) / Write (Configuration) operations Heterogeneous Processor support lots of legacy IP Nexus - CPU/SoC architecture agnostic standard (15+ different architectures) Nexus - Implicit multi-core support Long Thin Wire for debug Nexus - High speed SERDES (Aurora) / 2 Wire JTAG(IEEE ) Interface Leverage mature technologies Nexus original Spec Developed in 1999 Aligned with other standards bodies , , MIPI, Power.org, OCP-IP Nexus - Default standard use in US Automotive electronics Multiple tools Sources Nexus - Support from range of vendors in the tools community Nexus IEEE-ISTO 5001 Standard - Industry consortia. 6

7 A system level Nexus 5001 Subsystem 1 core Trace RAM configuration Processor Cross-triggers JTAG chain core core core Subsystem 2 Local Nexus JTAG 2-wire (1149.7) Debug Control Messages Subsystem 3 Trace Combiner Router Aurora Serdes Channels Debug/Trace Data Messages Subsystem 4 Trace Buffer Bidirectional For calibration capabilities 7

8 Multiple Concurrent Instruments Per Nexus Interface 8

9 Nexus interfaces include control and data options Core instruments Trace Data Calibration 9

10 Nexus interfaces /.7 Core instruments Trace Data Calibration 10

11 What is Interface Originally developed by MIPI T&DWG Supports 2-wire JTAG interface (TCK, TMSC). IO Complaint to IEEE (TCK, TDI, TDO, TMS, TRST) Supports diverse parallel and serial JTAG data configurations 11

12 IEEE Class Features Advanced Debug Features JTAG Extended Features JTAG Compliant Features Class 5- BDX Data Channels with 2 pins, custom pin support (CDX) Class 4-2 Pin Parallel (Star-2) Topologies Class 3 Parallel (Star-4) Scan Topologies Class 2 Chip bypass in a Series Scan Topology Class 1 Basic control and function extensions, power control Class 0 multiple on-chip TAPs with IEEE compatibility User Selectable addition of Advanced Debug Features 12

13 Nexus interfaces Data Options Core instruments Trace Data Calibration 13

14 What is Aurora Interface Allows upper layers Nexus 5001 protocols to use highspeed serial links. Aurora is a high-speed serial, link level interface that supports either a single or multiple lane channel The Aurora protocol defines the physical layer, the link layer, data striping for utilizing one or more lanes, and flow control scalable, lightweight, low-latency link-layer protocol open protocol - free of charge. transparent interface to the physical serial links, Supports LVDS type interface. 1 to 5 Gbps trace output - increased bandwidth through bonded lanes See Xilinx has Aurora Bus functional models available 14

15 Aurora Interface Signaling Core Wrapper Nexus Logic & Instruments Supports both Framed and Streaming transfer modes 15

16 Summarizing System Debug 16

17 Nexus 5001 Key Technical Points Packet based Debug Protocol Simpler Multicore support Configurable fields Predefined Debug Instruction set (TCODES) Instruction and Data Trace, register, and memory access commands In place support from leading commercial tool vendors Configurable for additional user/vendor defined messages Predefined Register Set (optional) Simplified core level integration JTAG compatible interface Support for both IEEE and standards Parallel interfaces options for data transfer Parallel bus (AUX ports) or SerDes compatible interface (Aurora) User defined channels for Output (Trace) and/or Input (Calibration) User defined mix and match of JTAG and parallel interfaces Ie. JTAG input for control, parallel output for trace

18 Nexus 5001 Benefits MCU Vendors Simplifies tools support Customer understanding and access of tools strategy Re-use reduces time/cost Leverage best in class tools Easier, porting of tools on new architectures standard methodology for development & production Trace without the bus (reduced pin overhead) Users Learning cycles tools and architecture(s) Quicker time to market Development tool reuse Proven capabilities - multiple architectures Single small foot print interface Real Time debugging, triggering and trace Tool Vendors Reduced development cost Rapid migration to new architectures Standard functions Opportunity to differentiate tools Ease in addressing new tool requirements High performance lower cost tools More information - nstollon@nexus5001.org This presentation will be posted later this month 18 18