ENABLING A NEW PARADIGM OF SYSTEM-LEVEL DEBUG PRODUCTIVITY WHILE MAINTAINING FULL IN-CIRCUIT EMULATION PERFORMANCE. CDNLive! Silicon Valley 2012
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1 ENABLING A NEW PARADIGM OF SYSTEM-LEVEL DEBUG PRODUCTIVITY WHILE MAINTAINING FULL IN-CIRCUIT EMULATION PERFORMANCE CDNLive! Silicon Valley 2012 Alex Starr March 13, 2012
2 INTRODUCTION About the author Alex is AMD s Hardware Emulation Architect, driving the emulation research and development initiatives for CPU, APU, and GPU products. Send questions to alex.starr@amd.com Acknowledgements: Brian Fisk & Eric White Emulation use at AMD More than 100 users across design engineering, platform engineering, product engineering, and software engineering. Emulation is being used to reduce product time to market Improved design health. Post-silicon infrastructure readiness. Software enablement. Been doing emulation for many years. Cadence Palladium technology introduced over six years ago. 2 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
3 PROBLEM STATEMENT Debugging designs on hardware emulators today is a challenge when compared with software simulation capabilities. Debugging becomes more and more challenging as design complexity increases. Large workloads, such as OS boots, driver testing, and application code make the problem even harder. Needle in a haystack: Where do I dump waves? The faster the emulation technology becomes, the worse the problem becomes. Bigger haystack! Users demanding more debug visibility. 3 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
4 THE TRADITIONAL EMULATION DEBUG CYCLE Large workload debug might go something like this 1. I dumped waves, but missed the failure point. 2. I ll have to schedule my tenhour job and try again. 3. I ll have to figure out how to trigger in the right place. 4. The next available time on the emulator is next week. 5. Next week What was I doing again? 6. I dumped waves and missed the failure again! 4 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
5 WHAT S WRONG WITH WAVES? Industry solutions can generate waves with visibility of all nodes, which is great. Wave capture limitations: Wave capture depth typically small Speed of emulation while dumping waves Can be slower on some systems When using timing-sensitive dynamic targets, even greater restrictions exist: Design clocks must continue to run unhindered at full speed Possible to miss events for back-to-back wave dumps Users need more trace. However, having waveforms of all nodes for large multi-day workloads is too much data (for humans and tools/disks) 5 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
6 DYNAMIC TARGET EMULATION MODEL OVERVIEW Palladium Dynamic Targets PCIe speedbridge + misc. other signals Graphics & Multimedia Engines I/O Subsystem Fusion Controller Hub (SouthBridge) SATA Hard Disk DDR NorthBridge CPU Core CPU Core 6 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
7 WAVE DUMPING STRATEGIES Trigger Trace buffer depth No dynamic targets Clocks stopped between uploads Takes a long time Lots of disk needed Multiple trace uploads Trigger Trace buffer depth Timing-sensitive dynamic targets connected Clocks cannot be stopped Easy to miss point of failure Trace upload time 7 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
8 REQUIREMENTS FOR A NEW CAPABILITY Requirement Need to abstract data to a level relevant for end-user debug Need solution to function with dynamic targets Design clock cannot stop Need the ability to identify the location for a waveform dump Should not impact the emulation capacity requirements of designs significantly Should maintain existing in-circuit emulation speeds Save and restore continues to function as normal Capture all design nodes of significance needed for system-level debug We want to see all data associated with element being monitored Lossless capture, no missed events Architected such that it is portable across emulation platforms with minimal modification Easy automation of user actions based on monitored data No rebuild of databases required when adding monitors 8 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
9 MONITOR COMPARISONS Synthesizable RTL monitor QEL monitor Transactional streaming monitor Language HDL QEL (tcl) SDL (tdf) Description Output Format Pros Decoding internal DUT signals into humanconsumable formats. Used as foundation for improved monitoring by QEL and transactional streaming monitors. Pure TCL functions that run in the background periodically (as fast as 2 ms) and execute arbitrary QEL commands. Each monitor can optionally log output to a file or the QEL GUI window without blocking user input. HDL C++ Using in-circuit acceleration mode to stream data from RTL nodes to the SA workstation for decoding with a C++ process. Targeted to function in situations in which we do not want to stop the clock with dynamic targets attached. Waves. Logfiles. Logfiles, Transaction visualizer. Good if you want additional decoded data captured in waveforms. No hardware or build dependencies. Can iterate quickly on fixes, updates without recompile. Lossless monitoring. High-bandwidth cycleaccurate trace of activity without wave dumping or interruption. Visualization possible. Cons Increases design size. Careful of constructs. Possible to miss some events if polling too slow. Requires simulation acceleration card. Monitors themselves are not executed in an atomic nature design still running as commands execute. Need to deal with buffer flushing management. 9 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
10 DEBUG CAPABILITY: QEL MONITORS What are they? Pure TCL functions run in the background periodically (as fast as 2 ms) and execute arbitrary QEL commands Monitor can optionally log output to a file or the QEL GUI window without blocking user input QEL Monitor Architecture QEL Domain Palladium QEL Monitor A Can be created, enabled, disabled, or changed on the fly & can essentially have any number of them running concurrently Value: Provides medium-bandwidth periodic trace of activity without wave dumping or interruption Enables coarse-grained monitoring without any hardware or build dependencies Automation of sequence of user input events over time based on emulator conditions or SDL state possible Lightweight and very flexible, lots of potential uses Design Polling, 1/2 sec Polling, 2 sec Cycle accurate QEL Monitor B SDL Instances Notes: Polling-based, not event-based Monitors themselves are not executed in an atomic nature design still running as commands execute Dependency on TCL event loop will not run during download or when GUI is otherwise frozen 10 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
11 TRANSACTIONAL STREAMING MONITOR SYSTEM Palladium Dynamic Targets PCIe speedbridge + misc. other signals Graphics & Multimedia Engines PCIe I/O Subsystem Fusion Controller Hub (SouthBridge) Synthesizable RTL Monitors MC SATA Hard Disk DDR DDR CCI NorthBridge SA Workstation RIP GPR CPU Core RIP GPR CPU Core BFM Transactor Interface SimAccel connection C++ Transaction Decode Process CAKE Domain SCM Domain 11 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
12 TRANSACTION STREAMER ARCHITECTURE BFM Transactor Interface CAKE SCM Clock Domain CAKE Clock Domain Synthesizable Monitor Block Transaction Capture Transactor Streamer FIFO Transactor Buffer Batch Send (Full or Flush) DAS Interface: SCEMI DPI / Pipes CTB C++ Decode/interpret data Transactor Control CAKE Lossless monitoring Timestamp Flush Visualization possible 12 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
13 TRANSACTION VIEWER : CpuReq Addr=fe c Cmd=8 CoreId=0 Tag= : CpuReq Addr=fe c Cmd=b CoreId=0 Tag=2f : CpuReq Addr=fe c Cmd=8 CoreId=0 Tag= : CpuReq Addr=fe Cmd=8 CoreId=0 Tag= : CpuReq Addr=fe c Cmd=b CoreId=1 Tag=2f : CpuReq Addr=fffffff0 Cmd=9 CoreId=0 Tag= : CpuReq Addr=ffff0000 Cmd=9 CoreId=0 Tag= : CpuReq Addr=ffff0000 Cmd=9 CoreId=0 Tag= : CpuReq Addr=ffff0010 Cmd=9 CoreId=0 Tag= : CpuReq Addr=ffff0020 Cmd=9 CoreId=0 Tag=0 Data from all monitors is imported into an AMD internal transaction database : thread:0 rip: fff : thread:0 rip: ffaa : thread:0 rip: : thread:0 rip: c5fc : thread:0 rip: c : thread:0 rip: c : thread:0 rip: c : thread:0 rip: c60e import Linked transactions Searchable Viewer enables an improved method of interpreting data 13 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
14 INTRODUCTION OF IN-CIRCUIT ACCELERATION (ICA) MODE FPGA Prototyping Palladium In-circuit Emulation Dynamic Targets In-circuit Acceleration DUT Speed Synthesizable Testbench Transactionbased Simulation Acceleration Signal-based Simulation Acceleration Software Simulation Debug Visibility 14 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
15 NEW DEBUG METHODOLOGY Use more abstract, userdigestible transaction data to pinpoint exact waveform trigger. Sometimes able to debug problem without any waves, especially if a workload problem (rather than design). Trigger Trace buffer depth More efficiently catch failure point in the narrow waveform trace window. First-time wave dump success! 15 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
16 SCORECARD Requirement QEL monitor Streaming transactional monitor Design clock cannot stop Need to abstract data to a level relevant for end-user debug Need solution to function with dynamic targets Need the ability to identify the location for a waveform dump Should not impact the emulation capacity requirements of designs significantly Should maintain existing in-circuit emulation speeds Save and restore continues to function as normal Capture all design nodes of significance needed for system-level debug We want to see all data associated with element being monitored Lossless capture, no missed events Architected such that it is portable across emulation platforms with minimal modification Easy automation of user actions based on monitored data No rebuild of databases required when adding monitors 16 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
17 THE NEW EMULATION DEBUG CYCLE Single debug iteration becomes more efficient: Debuggers have more data to go on at improved abstraction level. Able to jump to failure area with much higher degree of accuracy usually in one iteration. Large overall reduction in number of debug iterations. Traditional Iterations New Iterations Accelerated Debug 17 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
18 RESULTS Internal customer testimonials An issue we were debugging would have taken weeks to root cause without VLA. Just wanted to highlight another success story with VLA. Debug that would ve been drawn out took under two hours to narrow down and form a theory, which took us to root cause in another hour. And all we used was the GPR monitor!! Typically see multiple difficult to debug, critical path issues per project. Users are requesting this enhanced debug capability for all emulation builds. Benefits: Increase amount of time for other emulation activities Significantly reduce testplan execution time Increase confidence in design health Improve infrastructure readiness pre-silicon Testplan execution Major Debug Additional testplan execution Before After Emulation start Emulation end 18 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
19 FUTURE DIRECTION Roadmap of monitors: New designs have new interfaces that we plan to add into the system. Automatic analysis of monitor data streams: Interface to complex checkers/monitors that cannot be synthesized into emulators. Re-use of verification infrastructure, while optimizing for performance. Apply techniques to other areas: Performance and power event monitoring. Design throughput measurements. 19 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
20 Trademark Attribution AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners Advanced Micro Devices, Inc. All rights reserved. 20 Emulation system-level debug productivity CDNLive! Silicon Valley, March 2012
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