Design Verification Challenges Past, Present, and Future

Transcription

1 Design Verification Challenges Past, Present, and Future Wally Rhines Chairman and CEO Mentor Graphics Corp March 1, 2016

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3 Design Productivity Grew 5 Orders of Magnitude Since ,000,000,000,000, ,000,000,000,000 10,000,000,000,000 1,000,000,000, ,000,000,000 Quantity 10,000,000,000 1,000,000, ,000,000 10,000,000 1,000, ,000 10,000 Transistors Produced Total Electronic Engineers Source: Technology Research Group EDA Database, 1986, EDA TAM, 1989 & Gartner/Dataquest 2005 Seat Count Report, Gary Smith EDA, 2013 Seat Count Analysis, VLSI Research, Transistors Produced Analysis 3

4 Cost Learning Curve Continues With or Without Moore s Law 3.E+01 Revenue/Transistor ($) 2.E-01 8.E-04 4.E-06 2.E-08 1.E E E E E E E E E E+20 Cumulative Transistors Shipped Semiconductor Learning Curve Adjusted for Inflation 4 Source: VLSI Research, SIA, Federal Reserve Note: Revenue adjusted for Inflation

5 Cost of EDA Software Decreases at the Same Rate as the Revenue per Transistor 1.E-04 Learning Curve Revenue ($)/Transistor Revenue per Transistor 1.E-07 1.E-10 1.E-13 1E+13 1E+15 1E+17 1E+19 1E+21 Note: EDA Cost Consists of EDA License and Maintenance revenue adjusted for Inflation Cumulative Transistors Shipped 5 Source: VLSI Research, EDAC Market Statistics Service, Federal Reserve

6 IP Reuse Has Driven a Large Share of Recent Design Productivity Gains 100 Number of IP Blocks/Chip * 2016* 2017* 2018* 6 Source: Semico Research Corp. *Forecast

7 Demand for Design Engineers Grows Slowly Mean Peak Number of Engineers/Design Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

8 Verification Engineers Increase at 3.5X the Rate of Increase of Designers Mean Peak Number of Engineers/Design Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

9 Upper Bound of Verification Cycle Requirements Increases 2 x ASIC SRAM ASIC ASIC DSP ANALOG x = memory bits + flip-flops + latches + I/O 9

10 VERIFICATION 0.0

11 VERIFICATION 0.0 Large Scale Integration (LSI) Evolves to VLSI SSI/MSI design and verify Manual design and layout Fabricate it Test it Re-design it Repeat 11

12 VERIFICATION 0.0 Transistor-Level Simulation CANCER Ron Roher SPICE Simulation Program with Integrated Circuit Emphasis L.W. Nagel and D.O. Pederson Presented April 12,

13 Larger Designs Required Gate-Level Simulation VERIFICATION 0.0 Mentor Graphics 1982 IDEA Station QuickSim QuickSim Performance: Workstation dependent Capacity: Workstation dependent 100K+ gates when gate-level models are used, much larger when functional or behavioral modeling methods are used 13 Source: Mentor Graphics

14 VERIFICATION 1.0

15 VERIFICATION 1.0 VHDL Hardware Description Language Source: IEEE Design & Test 1986 Source: DAC 1983 Source: IEEE Design & Test 1986 IBM, Texas Instruments & Intermetrics awarded contract 1983 VHSIC Hardware Description Language VHDL 7.2 released in 1985 VHDL became IEEE Standard 1076 in 1987 Source: IEEE

16 VERIFICATION 1.0 Verilog Hardware Description Language Gateway Design Automation 1985 Verilog HDL created by Phil Moorby in 1984 Acquired by Cadence in 1989 Verilog became IEEE Standard 1364 in Source: IEEE Design & Test of Computers, August 1985

17 VERIFICATION 1.0 Ever-Improving Compute Performance 17 Source:

18 RTL Simulation Accelerates Independent of Hardware Performance VERIFICATION Relative Performance (Q1) 2002(Q4) Source: Mentor Graphics

19 VERIFICATION 2.0

20 VERIFICATION 2.0 Language Evolution Simulation Era RTL Era Testbench Era HILO System HILO Verilog Verilog 2001 SuperLog System Verilog Vera e SystemC VHDL 83 VHDL 87 VHDL 93 VHDL 2002 VHDL 200x 20 Source: Mentor Graphics

21 VERIFICATION 2.0 Industry Converges on IEEE 1800 IEEE unifies Verilog standards efforts Richard Goering 6/24/2004 3:00 PM EDT SANTA CRUZ, Calif. Putting to rest fears of a Verilog language schism, the IEEE has decided to form a single working group that will encompass both SystemVerilog and the further evolution of the IEEE 1364 Verilog language standard. The move follows criticisms of Accellera s decision to take SystemVerilog to a new IEEE working group rather than the existing 1364 committee. In May, Accellera voted to take SystemVerilog to a new working group under the 21

22 SystemVerilog Becomes Mainstream Verification Language VERIFICATION % Design Projects 70% 60% 50% 40% 30% 20% % 0% VHDL Verilog Synopsys Vera System C SystemVerilog Specman e C/C++ OTHER Testbench * Multiple answers possible 22 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study - Excludes FPGA Devices

23 VERIFICATION 2.0 Standardization in Base Class Libraries 70% 56% growth Design Projects 60% 50% 40% 30% 20% % 0% Accellera UVM OVM Mentor AVM Synopsys VMM Synopsys RVM Cadence erm Cadence URM None/Other 23 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study - Excludes FPGA Devices

24 VERIFICATION 2.0 Verification Is a $1 Billion Market $724M $109 $188 $1,002M $143 $ CAGR Total 9% Formal 7% Emulation 16% $427 $515 Simulation* 5% *Includes dynamic RTL simulation tools Source: EDAC Market Statistics Service

25 VERIFICATION 3.0

26 The Emergence of New Layers of Verification Requirements Brought on by the System Era Software Domains Verification Layers Security/Safety Domains Power Domains Performance Domains Clock Domains Functional Domains 26

27 Emergence of Multiple Engines to Address These New Requirements Virtual Prototype Formal Simulation Emulation FPGA Prototype 27

28 Virtual Prototype Formal Simulation Emulation FPGA Prototype 28

29 Integrating Cross-Domain Systems: An Automotive Example Software Market Drivers Hardware Complexity High Cost of Failure IVI Driver Information ADAS Telematics Car Network Integrating cross-domain systems exposes emergent behavior earlier in the design process; Functional, Performance, Safety/Security, Connectivity 29

30 Power Verification Challenges Hypervisor/OS control of power management Application-level power management Operation in each system power state Interactions between power domains Hardware power control sequence generation Transitions between system power states Power domain state reset/restoration Power domain power down/power up 0% 10% 20% 30% 40% 50% 60% 70% 80% Design Projects * Multiple answers possible 30 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

31 Managed Power Growing at the Chip Level 19% Increase in Two Years 80% 70% Actively Manage Power No Power Management Design Projects 60% 50% 40% 30% 20% Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

32 Verification and Architectural Tradeoffs of Power/Performance Software SoC TLM Model TLM TLM TLM TLM SoC architecture tradeoffs Timing/ Power Analysis Explore IP micro-architecture alternatives RTL 32

33 Verification and Architectural Tradeoffs of Power/Performance C++ / SystemC Area or Power IP Block X RTL X Local Minimum Optimization Scope Global Minimum X Architectural Scenarios 33

34 Virtual Prototype Formal Simulation Emulation FPGA Prototype 34

35 Number of Clock Domains Increases with Design Size Number of Clock Domains < 5M 5-80M > 80M Gates 35 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

36 Application-Specific Formal Includes Checking Clock Domain Crossings Clock Domain A Clock Domain B Synchronizer Identify metastability issues for signals crossing multiple clock domains due to improper synchronization Now scales to the full chip level 36

37 Formal Property Checking Used for Larger Chips 40% 30% 37% Design Projects 20% 10% 15% 25% 0% < 5M 5M - 80M > 80M Design Size 37 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

38 Formal Technology Adoption 30% 25% % 25% 26% Design Projects 15% 10% 13% 21% 5% 0% Formal property checking Automatic formal applications 38 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

39 Today s Application-Specific Formal Identify Deadlock and Finite State Machine Design Issues Identify Full Chip SoC IP Connectivity Errors Improve Simulation Coverage by Identifying Unreachable Code Identify X-Propagation RTL Issues 39

40 Virtual Prototype Formal Simulation Emulation FPGA Prototype 40

41 Simulation Growth in Requirements Metrics Stimulus quality: Code coverage Design activity: Toggle coverage Design quality: Functional coverage, Assertions, System-level analysis Domains Gate level RTL Low power Analog-digital Stimulus Directed tests Constrained random Verification IP Graph based Software DUT VHDL, Verilog Environment Debug Capacity Data management Regression efficiency 41

42 What s Next: Answering System-level Questions With Data Mining and Analytics Q: Can you show me how often does a snoop request occur to a CPU master while that master is executing a WriteBack command? A: Exactly 35 times during test2_100ms and over 3000 for test2_full Count M 10M 15M 20M 25M 30M 35M 40M 45M 50M 55M Cycle 42

43 Virtual Prototype Formal Simulation Emulation FPGA Prototype 43

44 Pre-ICE Age 44

45 ICE Age Applications Age Test Bench Acceleration Age Physical Target Virtualization Age Basic Functionality CPU/GPU Networking Multimedia Storage Mobile Automotive IOT DFS ICE Age CPU/GPU

46 Emulation Grows as Clock-Speed Scaling Stalls Emulation Required to Extend Performance 46 Source: Nature.com Feb 2016

47 Acceleration Age Applications Age ICE Age Acceleration Age CPU/GPU Stimulus/ Tests 1 st Channel 2 nd Channel 3 rd Channel 4 th Channel 5 th Channel CPU/GPU Networking Multimedia Storage Mobile Automotive IOT DFS 16 th Channel DUT CPU/GPU

48 Virtualization Age Data Center Friendliness Virtualization Age ICE Age Global Access Virtual Transactors CPU/GPU CPU/GPU Networking Multimedia Storage CPU/GPU

49 Emulation Moves from Lab to the Data Center 49

50 Embedded Software Development Headcount Surges past Hardware Verification 800 Engineering Years Software Engineering Hardware Engineering nm 65nm 45/40nm 28nm 20nm 16/14nm 50 Source: International Business Strategies, Inc. (IBS), 2013

51 Emulation With Trace Makes Software Debug Interactive and Cost-Effective JTAG 1 MHz One user at a time Trace-Based MHz ~10 Simultaneous users TRACE FILE 51

52 Applications Age Applications Age Optimized Execution Power ICE Age Coverage/ Assertions Deterministic ICE SW Debug CPU/GPU Peripheral Solutions DFT Visualization Enterprise Server CPU/GPU Networking Multimedia Storage Mobile Automotive IOT Design for Security CPU/GPU

53 Virtual Prototype Formal Simulation Emulation FPGA Prototype 53

54 Regression Testing and Application Software Drive FPGA-Based Prototyping 54

55 FPGA Prototyping Challenges Other (Please specify) Lack of coverage metrics HW/SW co-debugging Internally stimulating (irritating) the design Stimulating the external ports of the design Time to bring up prototype Capacity Issues Performance Debug Visibility Clocking Issues Mapping ASIC into FPGAs 0% 10% 20% 30% 40% 50% 60% 70% 2014 Design Projects * Multiple answers possible 55 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

56 FPGA Prototypes Still Used for Regression Testing and Application Software Verification 45% 40% Design Projects 35% 30% 25% 20% 15% 10% % 0% Hardware/software co-verification HW Acceleration & Emulation FPGA prototyping 56 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

57 Emulation Usage Grows as Design Size Increases 60% 57% < 5M 5-80M > 80M Non-FPGA Study Participants 50% 40% 30% 20% 10% 18% 50% 32% 45% 28% 0% HW Acceleration/Emulation FPGA Prototyping 57 Source: Wilson Research Group and Mentor Graphics, 2014 Functional Verification Study

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59 Historically Each Engine Required its Own Verification Environment Bringing Multiple Verification Silos Together 59

60 What Is Still Needed? Stimulus Measurement & Analysis Debug Users should not be able to tell if their job was executed on a simulator, emulator, or prototype Verification Infrastructure Bill Hodges, Intel PPA Austin MTV Conference December 2015 Virtual Prototype Formal Simulation Emulation FPGA Prototype An environment where the verification process is completely abstracted from the underlying verification engines 60

61 The Goal of Portable Stimulus STIMULUS SIMULATION EMULATION FPGA PROTOTYPE IP BLOCK SUBSYSTEM FULL SYSTEM 61

62 Evolution of the Portable Test Bench Validation Engineer C/C++ SW Test Engineer C/C++ Users Verification Engineer SystemVerilog SW Developer Embedded C/C++ Architect SystemC Virtual Platform Simulation Emulation FPGA Prototype Platforms Silicon 62

63 Portable Stimulus Working Group Single input specification Enable test creation automation Reusable across all platforms Tools generate specifics 63

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66 Soon, the Internet of Things Will Expand the Security Need to Almost Everything We Do *Rod Beckstrom, CEO and President of ICANN, former Director of the National Cyber Security Center 66 Source: Secure Connections for Smart Cars, Kurt Sievers NXP March2014

67 Levels of Security Concerns for Chip Designers Malicious Logic Inside Chip (Trojan Detection) Counterfeit Chips (Supply-Chain Security) Side-Channel Attacks (On-Chip Countermeasures) Use of hardened IP or altered design to resist attack Simulation of attacks to identify weaknesses Over-produced, re-marked, cloned, recycled or otherwise unauthorized ICs Distributed through unauthorized distributors Motivated by Profit Static Tests Analyze RTL (unknown unknowns) Dynamic Detection Insertion of logic to analyze runtime activity 67

68 EDA Will Become the Core of the Solution VERIFICATION TRADITIONAL ROLE Verifying that a chip does what it is SUPPOSED to do EMERGING NEW ROLE Verifying that a chip does nothing it is NOT supposed to do 68

69 Is The Desired Path The ONLY Path? AXI Bus PHY SDRAM AXI Bridge Ethernet Controller SDRAM Controller System Interconnect 0 RAM RAM DMA DMA Key Storage RAM System Interconnect 1 μc Encryption Engine 69

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71 Safety-Critical Design and Verification No harm to systems, their operators, or to bystanders Certification standards ISO Automotive IEC Medical DO-254 Aerospace 71

72 ISO Functional Safety Standard Safe system development processes Provide evidence that all reasonable system safety objectives are satisfied Avoid risk of systematic failures or random hardware failures by appropriate requirements and processes 72

73 Requirements Tracking for Safety-Critical Design Auditor checks Each requirement verified Identify specific test used to verify it Automatic requirements tracking available for many years REQ 1 FUNC 1 FEATURE 1 REQ 2 Covers FUNC 2 FEATURE 2 REQ 3 FUNC 3 FEATURE 3 REQ 4 FUNC 4 FEATURE 4 REQ 5 Covers FUNC 5 FEATURE 5 Systems Specification Design Specification Design Implementation 73

74 Is your System Safe in the Presence of a Fault? Fault injection Determines if response of system matches specification, despite presence of faults Helps developers understand the effects of faults on target system behavior Assess overall risk Formal-based fault injection/verification Exhaustively verifies safety aspects of design due to faults 74

75 Summary Despite design re-use, verification complexity continues to increase at 3-4X the rate of design creation Increasing verification requirements drive new capabilities for each type of verification engine Continuing verification productivity gains require EDA to: Abstract the verification process from the underlying engines Develop common environments, methodologies and tools Separate the what from the how Verification for SECURITY and SAFETY is providing another major wave of verification requirements 75

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