Steps to run compxlib to compile Xilinx libraries in Modelsim SE 10.1 for EE101/EE201L/EE560 students as well as USC ITS
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1 Gandhi Puvvada Steps to run compxlib to compile Xilinx libraries in Modelsim SE 10.1 for EE101/EE201L/EE560 students as well as USC ITS 1 Finish installing Xilinx ISE 13.2 and ModelSim SE We assume that you have successfully installed and tested the above two tools. EE101 students should have installed ISE WebPACK 13.2 and EE201L/EE560 students should have installed ISE 13.2 (Logic Edition). All should have installed Modelsim SE The following procedure is common to all students. 1.2 This procedure is for compiling Xilinx libraries in ModelSim SE 10.1 and setting the Modelsim SE as the tool for simulation in the Xilinx ISE Since Modelsim SE is used on the PCs in OHE336/RTH/SAL machines, the administrators of the PCs in OHE336/RTH/SAL user rooms may please follow these steps. Also students who installed Modelsim SE (and not PE student edition) will follow these steps. 2 compxlib 2.1 The procedure is a little murky so please follow the steps carefully. 2.2 First set Modelsim SE as the default simulation tool in ISE Find the Modelsim execution path first. Right-click on the Modelsim desktop icon and select properties. In the properties dialog box, copy the executable path I have provided you a design "adder4bit_post_route_simulation". Place this design in C:\Xilinx_projects folder. Invoke Xilinx ISE Design Suite 13.2 and open this project. January 26, :52 am 1 / 8 C Copyright 2012 Gandhi Puvvada
2 2.2.3 In the ISE Project Navigator window, go to Edit => Preferences => ISE General => Integrated Tools". In the field, Model Tech Simulator, paste the Modelsim execution path you copied a little before, click "Apply" followed by "OK". Verify again by opening this dialogue box. January 26, :52 am 2 / 8 C Copyright 2012 Gandhi Puvvada
3 2.2.4 Also set Modelsim as the default simulator in the Design Properties dialog box. In the implementation view, right click as shown below and select Design properties. 2.3 Now let us do the compilation of the xilinx libraries in Modelsim SE Open the command line window on your PC. Start => All Programs => Accessories => Command Prompt In the command window change directory and invoke compxlib. Note: If your system is a 32-bit system, you would change directory to nt instead of nt If the GUI in the next section does not let you select ModelSim SE simulator, then close the GUI and go back to the command prompt and type exactly as given below at the above prompt. (Note: you can type compxlib - help and it displays what switches mean what.) compxlib -s mti_se -p C:\modeltech64_10.1\win64\ -l all -arch spartan3e - arch spartan6 -arch spartan6l -lib all -w -verbose The above replaces the next 5 GUI screens. January 26, :52 am 3 / 8 C Copyright 2012 Gandhi Puvvada
4 I have chosen "Both VHDL and Verilog" while writing this installation note. ITS will also choose this option. EE101/EE201L students can choose just Verilog. EE560 EE101/EE201L Spartan3E and the Spartan6 are enough for students January 26, :52 am 4 / 8 C Copyright 2012 Gandhi Puvvada
5 2.3.5 January 26, :52 am 5 / 8 C Copyright 2012 Gandhi Puvvada
6 The displays in this step and next step will be slightly different for EE101/EE201 students as they selected just "Verilog" and not "Both VHDL and Verilog" in a prior step. January 26, :52 am 6 / 8 C Copyright 2012 Gandhi Puvvada
7 2.3.8 After about 15 minutes, it finishes compilation. Scroll down to see the following You can use Windows explorer to see that several files are produced under each of these two directories C:\Xilinx\13.2\ISE_DS\ISE\verilog\mti_se\10.1\nt64\ C:\Xilinx\13.2\ISE_DS\ISE\vhdl\mti_se\10.1\nt64\ 3 Now verify by performing a Post- Place & Route simulation in ISE. January 26, :52 am 7 / 8 C Copyright 2012 Gandhi Puvvada
8 A selected portion of the waveform is displayed below. Notice the actual delays of the gates and interconnect causing transitional values in the waveform which confirms that the delays of the actual xilinx components were used by the simulation. This means that our compilation was successful! 4 Celebrate your successful completion of compiling xilinx libraries using modelsim SE. January 26, :52 am 8 / 8 C Copyright 2012 Gandhi Puvvada
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Lab 1 You may work in pairs or individually on this lab Lab Objectives Learn about the equipment we will be using and how to handle it safely. Learn the basics of using Xilinx ISE to develop hardware designs
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DEPARTAMENTO DE TECNOLOGÍA ELECTRÓNICA ESCUELA TÉCNICA SUPERIOR DE INGENIERÍA INFORMÁTICA Introduction to Verilog and XILINX Lab Session Computer Structure WARNING: A written solution of the preliminary