Extending Rocket Chip with Verilog Peripheral IPs

Transcription

1 Extending Rocket Chip with Verilog Peripheral IPs Wei Song ( 宋威 ) Former hardware designer for lowrisc (v0.1 v0.4) 8 th September, 2018

2 lowrisc Project lowrisc is a not for profit organization from the University of Cambridge. Provide open-source and free SoCs. Linux capable. Highly customizable. Based on Rocket-chip (RV64G). Do not enforce the use of Chisel. Encapsulated Chisel islands of Rocket and caches. SystemVerilog top-level and interconnects. SystemVerilog AXI interfaces for peripheral IPs. 2

3 lowrisc SoC Today s topic: A generic and extendable AXI interface. 3

4 Rocket s Way of Adding Peripherals Each peripheral is wrapped by a TileLink Node, either an AXI4Port or a dedicated TLNode. The peripheral s parameter is backpropagated to each L1 cache and the global device tree. L1 cache can check IO access violations accordingly. Example memory map: bootrom: 0x x RX RTC: 0x x WR uart: 0x x WR bram: 0x x WRX Access to 0x would cause a synchronous exception in L1 $. 4

5 What lowrisc Expects A single AXI port is exposed. Peripherals can be attached to this single AXI bus using Verilog. Peripherals parameters are still backpropagated to the global device tree and all L1 $. Using AXI4MMIOPort provided by Rocket-chip: bootrom: 0x x RX RTC: 0x x WR AXI: 0x x WRX (shared by UART and BRAM) - UART 0x x WR - BRAM 0x x WRX Access to 0x would NOT cause any exception in L1 $! 5

6 The Problem The AXI4MMIOPort is by default represented by a single node in the device tree and address map. To use this node, end user needs to: Manually calculate the combined address map for the IO bus. Manually allocate interrupt lines. No direct method to add device into the generated device tree. Our solution: Extend the diplomacy package to implement an AXI4VirtualBusNode which is the root of a virtual tree representing the IO bus. This AXI4VirtualBusNode can automatically derive the parameters, add nodes in the device tree and connect interrupts. It also produces an AXI4 port like the AXI4MMIOPort for the external Verilog peripherals. 6

7 Overview of Diplomacy Diplomacy is a framework for negotiating the parameterization of protocol implementations. Compile time negotiation of parameters. Every agent is a diplomacy node. Node is a software entity rather than a real hardware module. 7

8 Virtual Bus AXI4VirtualBusNode: Produce an AXI port to the external Verilog and act as the root diplomacy node for the external AXI bus. AXI4VirtualSlaveNode: For each peripheral added to the global configuration, the SoC generator adds a slave node accordingly. The virtual diplomacy tree back-propagates address map, interrupts for the global device tree similar to normal diplomacy nodes. 8

9 Implementation of Virtual Nodes TileLink MixedNode is the common base class (BaseNode, InwardNode, OutwardNode) > MixedNode Bus(crossbar) MixedNode > MixedNexusNode > NexusNode > TLNexusNode Peripheral device MixedNode > SinkNode > AXI4SlaveNode lowrisc extension VirtualNode is the common base class (BaseNode, InwardNode, OutwardNode) > VirtualNode Remove the bundle connection Bus(port) VirtualNode > VirtualBusNode > AXI4VirtualBusNode Produce a port Peripheral device (diplomacy node only) VirtualNode > VirtualSlaveNode > AXI4VirtualSlaveNode 9

10 Global Configuration // define a peripheral case class ExSlaveParams( name: String, device: () => SimpleDevice, base: BigInt, size: BigInt, resource: Option[String] = None, interrupts: Int = 0, burstbytes: Int = 64, // needs to be set >= 64 readable: Boolean = true, writeable: Boolean = true, executable: Boolean = false ) // a collection of all Verilog peripherals case class ExPeriperalsParams( beatbytes: Int, idbits: Int, slaves: Seq[ExSlaveParams] ) Define the parameters of a single peripheral Collect all peripherals in a global object 10

11 Chip Generator trait HasAXI4VirtualBus extends HasPeripheryBus { val mmio_axi4 = AXI4VirtualBusNode( ) p(experiperals).slaves.foreach( d => { val slave = AXI4VirtualSlaveNode( Seq(AXI4SlavePortParameters(slaves = Seq(AXI4SlaveParameters( address = Seq(AddressSet(d.base, d.size - 1)), resources = d.resource.map(device.reg(_)).getorelse(device.reg), )), beatbytes = p(experiperals).beatbytes ))) slave :*= mmio_axi4 if(d.interrupts > 0) { val intnode = IntInternalInputNode( ) ibus.fromsync := intnode }) AXI port Generate virtual node for each peripheral connect port mmio_axi4 := AXI4Buffer()(AXI4UserYanker()(AXI4Deinterleaver()(AXI4IdIndexer(p(ExPeriperals).idBits)( TLToAXI4(p(ExPeriperals).beatBytes)(pbus.toVariableWidthSlaves))))) } 11

12 Adding a UART class LoRCCoreplexModule[+L <: LoRCCoreplex](_outer: L) extends RocketCoreplexModule(_outer) with HasRTCModuleImp with HasMasterAXI4MemPortModuleImp with HasAXI4VirtualBusModuleImp with HasSlaveAXI4PortModuleImp with HasPeripheryBootROMModuleImp class WithUART extends Config(Parameters.empty) { SlaveDevice.entries += ExSlaveParams( name = "uart", device = () => new SimpleDevice("serial",Seq("xlnx,uart16550")), base = 0x , size = 0x , // 8KB interrupts = 1 ) } class LoRCNexys4Config extends Config( new WithUART ++ new WithBootRAM ++ new WithNBigCores(1) ++ new LoRCBaseConfig) Add VirtualBus into the cake pattern Write a configuration class for the UART Use the UART configuration 12

13 Conclusions Diplomacy is a powerful software package to enable compile time parameter negotiation, much powerful than the parameters in SystemVerilog. A diplomacy node is not necessarily attached to a Chisel hardware module. By extending the diplomacy package with some extension in the Rocket-Chip generator, we can easily support automatic device tree generation for Verilog peripherals. Diplomacy: 190 lines Rocket-Chip generator: 300 lines 13

14 Thank You! 14