RISC V - Architecture and Interfaces

Size: px

Start display at page:

Download "RISC V - Architecture and Interfaces"

Lucas Hodge
5 years ago
Views:

1 RISC V - Architecture and Interfaces The RocketChip Moritz Nöltner-Augustin Institut für Technische Informatik Lehrstuhl für Rechnerarchitektur Universität Heidelberg February 6, 2017

2 Table of Contents 1 Introduction 2 Structure 3 Interfaces 4 Conclusion Moritz Nöltner-Augustin 2 / 26

3 Table of Contents 1 Introduction 2 Structure 3 Interfaces 4 Conclusion Moritz Nöltner-Augustin 3 / 26

4 What is RISCV? Source: Open-source Instruction Set Architecture (ISA) One ISA to cover all computer devices 3 ISAs ( bits) Meant for implementation Modular Extensible Actively developed A good investment? Moritz Nöltner-Augustin 4 / 26

pendant of linux SiFive and Open-V create

processor IIT Madras creates a processor

5 Why should I care? lowrisc aims to create the processor pendant of linux SiFive and Open-V create custom silicon ETH Zurich and Università di Bologna create a state of the art microcontroller NVIDIA replaces Falcon processor IIT Madras creates a processor UC Berkeley uses it for reasearch Sources: [1] Moritz Nöltner-Augustin 5 / 26

6 Table of Contents 1 Introduction 2 Structure 3 Interfaces 4 Conclusion Moritz Nöltner-Augustin 6 / 26

7 What is RocketChip? BOOM FPU L1I$ L1D$ Tile1 RoCC Accel. Rocket FPU L1I$ L1D$ Tile2 RoCC Accel. L2$ Bank L1toL2 Network L2toIO Network A B C D E F Core Cache RoCC TIle TIleLink Periph. TileLink/AXI4 Bridge AXI4 Crossbar DRAM Controller High- Speed IO Device AHB & APB Peripherals Source: [2] Moritz Nöltner-Augustin 7 / 26

8 How can I use RocketChip? git clone cd rocket-chip #git checkout boom git submodule update --init --recursive # Now the repo is about 3GB cd riscv-tools export RISCV=/path/to/toolchain/install export PATH="${PATH}:$RISCV/bin"./build.sh # Takes about 45 min # The toolchain is another 800MB cd../emulator make run CONFIG=BOOMConfig make run CONFIG=ExampleSmallConfig cd../vsim make -jn CONFIG=ExampleSmallConfig # about 20 min Source: Collected from [3] and [4] Moritz Nöltner-Augustin 8 / 26

9 What can be configured? A selection from $(ROCKET-CHIP)/src/main/scala/coreplex/Configs.scala: Tile (RC Boom): Caches: Uncore: Instruction width IFetch width Use debug #Breakpoints #Perf. Counters FPU key Mult. div. key Use atomics #Sets #Ways #TLB-Entries #row bits #id bits split metadata ECC code Replacement policy TileLink config L1toL2 config Broadcast config Banked L2 config Bootrom #Tiles $block #bytes Build Core? Moritz Nöltner-Augustin 9 / 26

10 How to configure RocketChip? /1 $(RC)/src/main/scala/coreplex/Configs.scala: case CacheBlockBytes => 64 case CacheName("L1D") => CacheConfig( nsets = 64, nways = 4, rowbits = site(l1tol2config).beatbytes*8, ntlbentries = 8, cacheidbits = 0, splitmetadata = false)... class WithL1ICacheSets(sets:Int) extends Config((site,here,up)=>{ case CacheName("L1I")=>up(CacheName("L1I"), site).copy(nsets=sets) }) // Likewise for nways class WithCacheBlockBytes(linesize:Int) extends Config((site,here,up)=>{ case CacheBlockBytes => linesize }) Moritz Nöltner-Augustin 10 / 26

11 How to configure RocketChip? /2 $(ROCKET-CHIP)/src/main/scala/rocketchip/Configs.scala class DualCoreConfig2way extends Config( new WithNCores(2) ++ new WithL1ICacheWays(2) ++ new WithL1ICacheSets(32) ++ new WithCacheBlockBytes(64) ++ new WithL2Cache ++ new BaseConfig) class DualCoreConfig4way extends Config( new WithNCores(2) ++ new WithL1ICacheWays(4) ++ new WithL1ICacheSets(64) ++ new WithCacheBlockBytes(32) ++ new WithL2Cache ++ new BaseConfig) Moritz Nöltner-Augustin 11 / 26

12 How to configure RocketChip? /2 $(ROCKET-CHIP)/src/main/scala/rocketchip/Configs.scala class DualCoreConfig2way extends Config( new WithNCores(2) ++ new WithL1ICacheWays(2) ++ new WithL1ICacheSets(32) ++ new WithCacheBlockBytes(64) ++ new WithL2Cache ++ new BaseConfig) class DualCoreConfig4way extends Config( new WithNCores(2) ++ new WithL1ICacheWays(4) ++ new WithL1ICacheSets(64) ++ new WithCacheBlockBytes(32) ++ new WithL2Cache ++ new BaseConfig)... cd rocket-chip/vsim make -j5 CONFIG=DualCoreConfig2way... make -j5 CONFIG=DualCoreConfig4way Moritz Nöltner-Augustin 11 / 26

13 Cache Example, 2-Way index i 64bytes Address Mem-block i th line Cache-block 32sets Mem-block i th line Set 0 Cache-block Set 1 32sets tag[20:0] index[4:0] Tag Mem 0 Tag Mem 1 = Mem-block i th line = or hit Main Memory Cache Address Logic Moritz Nöltner-Augustin 12 / 26

14 Cache Example, 4-Way index i 32bytes Address Mem-block i th line Mem-block i th line Cache-block Set 0 Cache-block Set 1 Cache-block 64sets 64sets 64sets tag[20:0] index[5:0] Tag Mem 0 Tag Mem 1 = Tag Mem 2 = Tag Mem 3 = Mem-block i th line Set 2 = Main Memory Cache-block Set 3 Cache 64sets Address Logic or hit Moritz Nöltner-Augustin 13 / 26

15 Results: Module ICache_icache (2 ways, 32 sets, 64 bytes) module tag_array( // x1 input [4:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [20:0] RW0_wdata_0, input [20:0] RW0_wdata_1, output [20:0] RW0_rdata_0, output [20:0] RW0_rdata_1, input RW0_wmask_0, input RW0_wmask_1 ); reg [41:0] ram [31:0]; module _T_772( // x2 input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); reg [63:0] ram [255:0]; Moritz Nöltner-Augustin 14 / 26

16 Results: Module ICache_icache (4 ways, 64 sets, 32 bytes) module tag_array( // x1 input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [20:0] RW0_wdata_0, input [20:0] RW0_wdata_1, input [20:0] RW0_wdata_2, input [20:0] RW0_wdata_3, output [20:0] RW0_rdata_0, output [20:0] RW0_rdata_1, output [20:0] RW0_rdata_2, output [20:0] RW0_rdata_3, input RW0_wmask_0, input RW0_wmask_1, input RW0_wmask_2, input RW0_wmask_3 ); reg [83:0] ram [63:0]; module _T_850( // x4 input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); reg [63:0] ram [255:0]; Moritz Nöltner-Augustin 15 / 26

17 Table of Contents 1 Introduction 2 Structure 3 Interfaces 4 Conclusion Moritz Nöltner-Augustin 16 / 26

18 RocketChip Interfaces clock reset io_interrupt_0_0 io_interrupt_0_1 TileLink TileLink io_mem_axi4_0 io_mio_axi4_0 ExampleRocketTop Moritz Nöltner-Augustin 17 / 26

19 RocketChip Interfaces clock reset io_interrupt_0_0 io_interrupt_0_1 451 signals per TileLink TileLink: Data + Opcode 282 signals per AXI interface io_l2_axi4_0 optional TileLink io_mem_axi4_0 TileLink io_mio_axi4_0 ExampleRocketTop Signal Bundle Write Address Channel Write Data Channel Write Response Read Address Channel Read Data Channel (Low Power Interface) Prefix _aw_ _w_ _b_ _ar_ _r_ _c_ Moritz Nöltner-Augustin 17 / 26

20 AXI Read Source: Taken from [5] Moritz Nöltner-Augustin 18 / 26

21 AXI Write Source: Taken from [5] Moritz Nöltner-Augustin 19 / 26

22 AXI Features Burst up to 256 transfers Memory attributes Transaction buffering Privileged, secure, instruction bits Transaction IDs Exclusive Access Atomicy size Quality of Service signals Moritz Nöltner-Augustin 20 / 26

23 TileLink: Inter-tile cache coherence network Agents Client Request/hold $ block Manager Oversee permission and data flow Channels Aquire Start read/write uncached Probe Check if client has $-block/revoke permissions Release Free data/write back Grant Provide data/permissions Finish Final acknowledgement from requestor Refer to the specification for definitions of the exact operations Moritz Nöltner-Augustin 21 / 26

24 TileLink: Operations Memory Manager Client0 Client1 Client2 Moritz Nöltner-Augustin 22 / 26

25 TileLink: Operations Memory A G Manager Client0 A G F Client1 P R Client2 Request Moritz Nöltner-Augustin 22 / 26

26 TileLink: Operations Memory A G R G Manager A R G Client0 G F Client1 P R Client2 Request Release Moritz Nöltner-Augustin 22 / 26

27 TileLink: Operations Memory A G R G Manager A R G Client0 G F Client1 P R Client2 Request Release Manager Don t accept transactions for in-flight blocks Client Don t release block with outstanding voluntary write-back Moritz Nöltner-Augustin 22 / 26

28 RocketChip Interfaces Source: Clipped from [6] Moritz Nöltner-Augustin 23 / 26

29 Table of Contents 1 Introduction 2 Structure 3 Interfaces 4 Conclusion Moritz Nöltner-Augustin 24 / 26

30 Conclusion RISC-V is here to stay RocketChip generates SoC Can use Rocket or Boom Lots of configuration options Chisel is hard to read Generated Verilog is worse RocketChip exposes AXI Many standard AXI IP Moritz Nöltner-Augustin 25 / 26

31 References Some users of the RISC-V ISA lowrisc: SiFive: Open-V: Pulp: IID Madras: Nvidia: UC Berkeley: Asanović, Krste/Avizienis, Rimas/Bachrach, Jonathan et at. (2016) The Rocket Chip Generator. Technical Report No. UCB/EECS , EECS Department, University of California, Berkeley. The RocketChip github pages The Berkeley Out Of Order Machine github page AXI Reference Guide, Xilinx Xuan Guo, Nathanael Davison, Profir-Petru Partachi, Alistair Fisher (2016) Technical report from the lowrisc Summer Internship AMBA AXI and ACE Protocol Specification, ARM Limited The TileLink Specification, Version Moritz Nöltner-Augustin 26 / 26

32 End Time for your questions Moritz Nöltner-Augustin 26 / 26

COMPUTER technology has seen the rise and fall of

COMPUTER technology has seen the rise and fall of ADVANCED SEMINAR COMPUTER ENINEERIN, UNIVERSITY OF HEIDELBER WT16/17 1 RISC-V Architecture and Interfaces The Chip Moritz Nöltner-Augustin University of Heidelberg, ZITI Abstract This paper gives a short