SITAL Technical Notes

Transcription

1 w Using Xilinx Core Generator in HDL Designer-ModelSim-Leonardo VHDL Desgin Flow SITAL Technical Notes Using Xilinx Core Generator in HDL Designer-ModelSim-Leonardo VHDL Desgin Flow 1

2 NOTE: This document is relevant for Xilinx ISE v4.1i and further versions. For other version please contact SITAL Technology. This document explains how to use a Xilinx Core Gen Model in HDL Designer for behavioral simulation and how to synthesize it as a black box in Leonardo Spectrum. Followo these steps: a) Open the Xilinx CORE Generator Interface from the tools menu in the design browser of the HDL Designer : b) Choose a library for the generated model from a pulldown list of existing libraries,and then press the Invoke CORE Generator button. 2

3 c) After the CORE Genrerator finish to generate the requested core it will appear as a component in the chosen library. 3

4 d) In order to use the Xilinx CORE Generator,you must compile the XilinxCoreLib library and the Unisim library first.these libraries should be compiled in Modelsim and refer as foreign libraries in the HDL Designer library mapping. e) Please do the following steps to generate the UniSim and the XilinxCoreLib Libraries: 1. Invoke the ModelSIM Simulation tool. 2. Within the Transcript text window do the following: 3. Change directory to.\xilinx\vhdl\src\unisims. 4. Execute the following commands in ModelSIM: vlib unisim vmap unisim unisim vcom -work unisim unisim_vpkg.vhd vcom -work unisim unisim_vcomp.vhd vcom -work unisim unisim_vital.vhd 5. Change directory to.\xilinx\vhdl\src\xilinxcorelib. 6. Execute the following commands in ModelSIM: vlib xilinxcorelib vmap xilinxcorelib xilinxcorelib vmap unisim <path_to_your_compiled_unisim> (like: \Xilinx\vhdl\src\unisims\unisim>) 7. From Windows Explorer, Verify that the following file exist:.../xilinx/vhdl/src/xilinxcorelib/vhdl_analyze_order 8. When you open this file list, you can see that the first text lines are : # VHDL Simulation file list. Files are listed in the order they should be # analyzed in. If file F1.vhd is dependent on file F2.vhd, then file F2 will be # listed before F1. # Note that all file names have been written in lower case. 9. Delete those text liens and save this file list, 10. Go back to the ModelSIM Transcript window. 11. Execute the following command in ModelSIM: vcom -work xilinxcorelib -f vhdl_analyze_order 12. The UniSim and the XilinxCoreLib Libraries are ready. 4

5 f) Now invoke the HDL Designer Series tool to map those libraries as a foreign librarirs. 1. From the option menu in the design browser,select Library Mapping : 2. In the Library Mapping window press the Add button and then press the Advanced button in the Add New Library Mapping window. 5

6 3. Set the 'Standard Library' switch(2), type the library name xilinxcorelib (1), and map it to the Modelsim xilinxcorelib compiled library location(3). Please be aware to the fact that the library xilinxcorelib is in the source directory XilinxCoreLib. The mapping should be to the compiled library i.e.:.\xilinx\vhdl\src\xilinxcorelib\xilinxcorelib 4. For mapping the unisim library, repeat steps In the Advanced Add Library Mapping window, set the 'Standard Library' switch(2), type the library name unisim (1), and map it to the Modelsim unisim compiled library location(3). Please be aware to the fact that the library unisim is in the source directory unisims. The mapping should be to the compiled library i.e.:.\xilinx\vhdl\src\unisims\unisim 6

7 5. Now you are ready to use the Xilinx CORE Generator model within the HDL Designer Series tool. NOTE : for gate-level simulation you have to create a compiled library called SimPrim. For instructions please refer to "xlinx_vital_sim.pdf in this site, and then do again steps f:1-3 in this document. 7

8 In order to synthsize a CoreGen Model you have to set it as a Black Box. Follow the next steps in order to set a Black Box. 1. Select the Relevant Model in the HDL Design browser. Open the mouse right button menu, and select the Don t Touch option. 2. Set the Don t Touch for Synthesis Compilation flag. 3. Now you can use the new symbol as a component in your diagram. 8

9 4. The EDN file that the Xilinx CoreGen tool generates is located in the side data window (you can see this file only when you click with your mouse the architecture of your model in the source window). 5. In order to run the P&R process, this EDN file is required. You have to place it (by copying or dragging it from the Side Data window to the LeonardoSpectrum Downstream window) together with the Leonrado synthesis result file (*.edf file) within the netlists directory, which has been created after Synthesis run flow of Leonardo (without run place and route in the same flow). 6. Now you can run your fitting tool. 9