The University of Toledo EECS:6660:0xxField Programmable Gate Arrays s09l1.fm - 1 Dr. A.D. Johnson

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1 EECS:6660:0xxField Programmable Gate Arrays s09l1.fm - 1 Lab Assignment #1 Due: Friday, February Introduction to Altera Quartus II Environment using VHDL Entry 1. Objectives - introduction to Quartus II, and terasic DE2 System tutorial documentation, - becoming familiar with the organization of Altera Quartus-II environment, - learning the Quartus-II implementation process based on a VHDL description ofdesign systems, - becoming familiar with the terasic demo board DE2, which fetures an Altera Cyclon 2 FPGA, - learning the implementation process on the terasic demo board DE2. 2. NE-1026 Prelab Assignment Use the NE-1026 Computer Lab to log on to your Engineering College Computing (ECC) account, and complete the Prelab Assignment. For the later work on Lab Assignment #4 use the NE-2036 FPGA Lab and log on to your FPGA Lab accounts. The work on this prelab assignment will require access to the Altera Quartus-II Interactive Tutorials, and the terasic DE2 FPGA board tutorials, which are available on the Engineering College Computing (ECC) file server. All results of the Prelab Assignment work must be accounted for in the text of the Prelab Assignment Report, which is a prerequisite for, and due at the beginning time of the work in the FPGA Lab session. 2.1 Creating the Directory for Lab Assignment #1 After logging in to an ECC general account, open a new Terminal window by executing: RMB Background Tools Terminal In the opened terminal window execute: tcsh source /eng/applications/altera/altera.csh cd ~/fpga/lab mkdir lab1 cd lab1 to create a directory named ~/fpga/lab/lab1, and make it the working directory in which the rest of this prelab assignment will be completed. 2.2 Accessing Quartus-II Environment FPGA vendor Altera provides an application named Quartus II, which is its version of an FPGA design and implementation environment equivalent to Xilinx s ISE. For its Quartus II application Altera provides interactive and static tutorials. Quartus-II interactive tutorials are accessible on the ECC server at: /eng/applications/altera/quartus To start the interactive tutorials execute,

2 EECS:6660:0xxField Programmable Gate Arrays s09l1.fm - 2 quartus after which nothing happens for about two minutes. At the end of those two minutes the Quartus window pops up, and on top of it a small dialog box with the option to create a new project now, for which select No 2.3 One time setting for the Browser The outcome of the next few steps will be remembered by Quartus, so they are one time only steps: From the top bar in the Quartus window select, Tools Options which brings up the Options window, in whiich under Category select, Internet Connectivity which brings up the Internet Connectivity window, in which enter into the "Web browser" text box: /eng/applications/firefox/firefox and then select, OK 2.4 Starting the Quartus-II Interactive Tutorial Session Interactive tutorials present a demonstyration of basic Quartus II environment capabilities. Under the best circumstances, students would want to eventually have played all of the six available Quartus-II interactive tutorials, but the first one is a mandatory part of this prelab assignment. Open the Help by selecting Help which drops down a menu from which select, LMB Tutorial which may open up the Default browser dialog box, in which select, Yes after which, depending on whether the Lab NE-1026 workstation which one is using has been freshly rebooted, or not, two different outcomes may occur Case 1: The Workstation has Not been Freshly Rebooted After Yes has been selected, Mozilla Firefox window pops up showing the Quartus II Interactive Tutorial window. One of the Interactive Tutorial window panes contains the Flash Player window with the upper left corner tab "Quartus II Tutorial", in which the text "Quartus II INteract..." keeps looping. This looping is a consequence of some software error involving the Adobe Flash Player installation. A workaround to stop the looping in the Flash window is as follows. From the top menu bar select, File New Tab after which the looping stops, and a new tab appears with the text: [Untiteld]", after which slect the initial tab, "Quartus II Interactive Tutorial" after which Interactive Tutoria stays steady in the Flash Player window with a small dialog box on top

3 EECS:6660:0xxField Programmable Gate Arrays s09l1.fm - 3 of it, in which select, Next after which the normal operation of the Interactive Tutorial starts Case 2: The workstation has been freshly rebooted When the Interactive Tutorial has not been run since the last reboot, it will run correctly the first time it is invoked. After the Interactive Tutorial has been run to the end, or has been stoppoed, Case 1 workaround procedure will have to be followed to rerun the Tutorial. Under the best circumstances, students would want to eventually have played all of the six available Quartus-II interactive tutorials, but the first one is mandatory for this prelab assignment. 2.5 Accessing the DE2 System Noninteractive Tutorials The terasic company, manufacturer of the protoboard DE2, has provided a series of noniteractive tutorials in portable data format (pdf), which describe in great detail the procedures of the same major phases of the FPGA design and implementation process which are introduced in the Quartus-II Interactive Tutorial. Following the static descriptions of procedures in these tutorials is advantagges when implementing student assignment specific designs. They can be followed from either a printed version, or just from an Adobe Reader window. These DE2-System tutorials are accessible on the ECC server at: /eng/applications/altera/de2_system_v1.6/de2_tutorials 2.6 Selecting the Particular Tutorial for Lab Assignment #1 This Lab assignment introduces the Quartus-II implementation process from a VHDL description of the logic/digital system. The particular tutorial to be followed: tut_quartus_intro_vhdl.pdf is located in the directory listed at the end of Section 2.5 above, and should be followed either from an Adobe Reader window, or from a printed copy. 2.7 following the DE2-System Tutorial: tut_quartus_intro_vhdl The execution of only the first six steps of the tut_quartus_intro_vhdl tutorial is a part of this Prelab Assignment. After the Step 6 of the Tutorial has been completed, make sure to save the Project which has been created in the course of work described in the tutorial! This saving step completes the Prelab Assignment. 2.8 PDF version of the Quartus-II tutorial There exist pdf versions of Quartus-II HDL tutorials; they can be found in the directory /eng/applications/altera/quartus7.2/common/help/tutorial Note that those are different from the Interactive QUARTUS II tutorial, and different from the DE2 SYSTEM noniteractive tutorials described in Sections 2.5 through 2.7 above. They are not a required exercise for Lab Assignment #1.

4 EECS:6660:0xxField Programmable Gate Arrays s09l1.fm NE-2036 FPGA Lab equipment Equipment to be used includes: - terasic demo board DE2, shown in Figure 4.1, - an x86 platform running under the Linux version Centos5, - USB Blaster cable, - power supply for the FPGA demo board DE2. Figure 3.1View of the DE2 FPGA protoboard. 4. NE-2036 FPGA Lab Assignment At the beginning of the Lab session, and before anything else should be attempted, a number of connections must be established between the FPGA board and other external equipment. These actions are described in sections 4.1 through 4.2. In the sequel, the sections 4.4 through 4.7 describe the interaction with the FPGA vendor software which leads to the programming of the FPGA and execution of the experimenting with the protoboard circuitry. 4.1 DE2 Connections A small number of connections ought to be established before proceding to other tasks.

5 EECS:6660:0xxField Programmable Gate Arrays s09l1.fm USB Blaster Connections The USB Blaster cable must be connected between: - the mini USB connector which is located next to the power jack on the DE2 FPGA board, - a USB connector on the computer Power Supply Connections DE2 FPGA proto board is powered by its own external power supply unit which should be connected as follows: - power supply s 5V DC cord plugged into the DC power jack on the DE2 board, - power supply s 120V AC cable into the power strip. The power is turned ON by pressing the red switch button on the DE2 board Selecting the Configuration Mode The configuration mode/procedure is determined by the set ting of the RUN/PROG switch: - for JTAG mode, which loads configuration data directly into the FPGA, set the RUN/PROG switch into position, RUN - for AS (Active Serial) mode, which loads configuration data into the configuration storage device named EPCS16, set the RUN/PROG switch into position, PROG. 4.2 Setting up the Application Software Environment To log in to a class account in the FPGA Lab, use the computer to which a DE2 FPGA board is connected. Then set up the environment which supports the application software by executing the following commands in the given order: source /eng/applications/altera/altera.csh cd lab/s09lab mkdir lab1s09 cd lab1s Copying the Prepared Configuration File from the ECC Environment The copying procedure will be as follows: scp <student_id>@ne eng.utoledo.edu:fpga/lab/s09lab/lab1s09/<filename>. where <student_id> equals the student s ECC account user name; followed by typing in the password password: ********* 4.4 Selecting the project On the command line type quartus.

6 EECS:6660:0xxField Programmable Gate Arrays s09l1.fm - 6 From the Quartus II window Tool bar select File Open Project which pops up the Open Project window in which select, light Open 4.5 Downloading the Configuration File Two basic ways of downloading the configuration file to an FPGA can be characterized as: - direct, where the contents of the configuration file are downloaded directly to the FPGA chip, - indiredct, where the contents of the configuration fiile are first downloaded to an intermediary storage memory device and from there to the FPGA chip Downloading the Configuration File directly to the FPGA - JTAG Mode Programming - Step 7.1 of the tut_quartus_intro_vhdl tutorial From the Quartus II window Tool bar, select: Tools Programmer which opens the Programmer window Quartus II - [Chain1.cdf], shown in Figure 41 of the tutorial, ] when the Chain1.cdf window appears, start following Section 7.1 of the tut_quartus_vhdl tutorial, by selecting: - in the Mode box select, JTAG then press the Hardware Setup button after which the window Hardware Setup pops up, in which click twice on the entry, USB-Blaster Close - next select, Add File which opens the Select the Programming File window in which select: light.sof OPEN which will open the window Chain1.cdf, in which verify that: - the proper device code is shown: EP2C35F672, - the box Program/Configure is chekmarked, - flip the RUN/PROG switch to RUN position, then select the button,

7 EECS:6660:0xxField Programmable Gate Arrays s09l1.fm - 7 Start and observe the stream of messages in the Message window, untill the appearance of the message: Info: Successfully performed operation after which proceed with experimenting using the demo board. Should the above message fail to appear, the configuration file has some error which must be corrected Downloading the Configuration File to the Flash Memory - Active Serial Mode Programming- Step 7.2 of the tut_quartus_intro_vhdl tutorial when the Quartus II window appears, select from itstoolbar: Assignments Device which opens the Settings- light window, shown in Figure 44 of the tutorial, ] when Settings- light window appears, click on the button: LMB Device & Pin Options which pops up the Device & Pin Options window, in which click on the tab, LMB Configuration which changes the view of the Device & Pin Options window, in whose Configuration device section: - check the Use configuration device selection box, - select the device EPCS16, - select OK, Which closes the Device & Pin Options window, after which select in the Settings- light window. OK To resssynthesize (recompile) the project select from the Quartus II Tool bar Processing Start Compilation which opens: - the Compilation Report with the Flow Summary in it, - small message window with the text: Full compilation successfull. Now select from the Quartus II window Toolbar: Tools Programmer which opens the Programmer window Quartus II - /export/czxb7r/fpga/lab1/light - light - l[ight.cdf], shown in Figure 41 of the tutorial, ] when the Chain1.cdf window appears, start following Section 7.1 of the tut_quartus_vhdl tutorial, by

8 EECS:6660:0xxField Programmable Gate Arrays s09l1.fm - 8 selecting: - in the Mode box select, Active Serial Programming which, in case when a change is being made from the previously used JTAG programming, will open the pop-up box which asks whether to clear all devices, after which select, Yes Next select, Add File which opens the Select the Programming File window in which select: light.pof OPEN which will open the window /export/czxb7r/fpga/lab1/light - light - l[ight.cdf], in which verify that: - the proper device code is shown: EPCS16, - the box Program/Configure box is chekmarked, - flip the RUN/PROG switch to PROG position then select the button, Start and observe the stream of messages in the Message window, untill the appearance of the message: Info: Successfully performed operation after which proceed with experimenting using the demo board. 4.6 Experimenting with the XOR circuit Experiment with the created XOR circuit by changing the switch positions on the protoboard DE2 by: - setting the switch DIP1 high, - setting the switch DIP2 high/low, and - setting the switch DIP1 low, - setting the switch DIP2 high/low. and watching the state of the LED connected to the output of the circuit. 5. Lab report To be considered complete the Lab4 report must contain the following, 1. Cover sheet - Lab style, filled out, 2. Description of steps performed in the Pre Lab assignment, and of their outcomes. 3. Description of steps performed during the Lab Experiment, and of their outcomes. 4. Table with the results of the XOR test which has been performed in the experiment.