Laboratory #Intro to Xilinx ISE and CR-2 Kit ECE 332
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1 Name: G Number: 1 Introduction Laboratory #Intro to Xilinx ISE and CR-2 Kit ECE 332 The purpose of this laboratory is to introduce the design tools used in ECE 332 lab. In this lab you will learn about creating new projects, adding existing source codes, implementing and programming the CPLD using Xilinx ISE 12.3 and Cool Runner-2 Utility Window. 2 Creating a Design Project To start Xilinx ISE 12.3 software, select: Figure 1: Xilinx ISE
2 ECE 332 Lab #1 2 Start All Programs Xilinx ISE Design Suite 12.3 ISE Project Navigator 2.1 Creating a New Project To select a new project: File New Project Enter a project name Lab 1 Demo and choose the appropriate design directory. Figure 2: Project Name and Location Window Select the Top-Level source type: HDL Click on Next button.
3 ECE 332 Lab # Selecting Device Properties Select the following options from the drop down menu Table 1: Device and Design-flow Information Property Name Value Product Category ALL Family CoolRunner2 CPLDs Device XC2C256 Package TQ144 Speed -7 Synthesis Tool XST (VHDL/Verilog) Simulator ISim (VHDL/Verilog) Preferred language VHDL Figure 3: Device and Design Flow Window 2.3 Project Summary The Project Summary window shows the selected design optiona and the added files. If there are any mistakes click on Back button and make the appropriate changes. If there are no mistakes then click on Finish button.
4 ECE 332 Lab #1 4 Figure 4: Project Summary 2.4 Adding New Source Codes To add a new source to the project, click on the New Source button on the left of the design window a shown in figure. Figure 5: Add New Source For the purpose of this lab there will be no new VHDL source codes created. Instead, you will be using existing VHDL source codes.
5 ECE 332 Lab # Adding Existing Source Codes You will be provided with VHDL source code file and a User Constraints File(UCF). In the Add Existing Source window To add an existing source to the project, click on the Add Copy of Source button on the left of the design window a shown in figure. Figure 6: Adding Existing Sources Select the VHDL source file and the UCF file. You can select and add multiple sources at a time. Figure 7: Adding Existing Sources Click on Open button after adding the sources.
6 ECE 332 Lab #1 6 ISE will open Adding Design Files window. This window displays whether the files were added successfully or not. If the files are added successfully then click on OK button. Error will occur only when files of undefined format are added. Figure 8: Adding Source Files 3 Implementing the Design 3.1 Checking Syntax In the Sources window (panel on left-top) select the file lab 1demo.vhd. The file name will be highlighted. Figure 9: Checking Syntax In the process window (panel on left-bottom) expand the Implement Design option by clicking the + sign. Expand the Synthesis option by clicking on + sign.
7 ECE 332 Lab #1 7 Double click on Check Syntax option. If the syntax of VHDL source file is correct a green-tick mark will appear as shown in the above figure. If the syntax is wrong a red-cross mark will appear. 3.2 Implementing the design In the process window double click on the Implement Design option or Select: Process Implement Top Module Figure 10: Implementing the Design There are three stages in implementing the design, Synthesis, Translate and Fit. The design should pass these three stages to successfully implement the described HDL module.
8 ECE 332 Lab #1 8 The generate Programming File option generates the so called *.jed file, which is used to program the CPLDs. 3.3 Viewing Reports To view synthesis reports expand Synthesis option double click on View synthesis report option. To view Translate reports expand Translate option double click on Translation report option. To view Fit reports expand Fit option double click on Fitter report option. 4 Programming the CPLD Ensure that the Cool Runner-2 CPLD board is connected to the computer via the USB cable (provided in your starter kit). Figure 11: Cool Runner-2 utility Window Start the Cool Runner-2 utility Window by selecting Start All Programs Digilent Tools Cool Runner-2 utility Window
9 ECE 332 Lab #1 9 Figure 12: Selecting the Programming File Click on the... button (browse) and navigate to the design folder you have specified in section 2.1. Select the *.jed file. Click on the Program button. A message will be displayed about the status of the programming of the CPLD at the bottom of the utility window, shown in 13. Figure 13: Programming the CPLD The board is programmed with the specified design. In the next lab you will learn about creating new source files, checking syntax, error correction and simulation of the HDL modules.
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University of Florida EEL 3701 Dr. Eric M. Schwartz Madison Emas, TA Department of Electrical & Computer Engineering Revision 1 5-Jun-17
Page 1/14 Example Problem Given the logic equation Y = A*/B + /C, implement this equation using a two input AND gate, a two input OR gate and two inverters under the Quartus environment. Upon completion