KUE-CHIP SS: (start/stop) SI: SP: for observation(ob) DBi. DBo. for observation(ob) for observation(ob) DBi. DBi. DBo.

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1 KUE-CHIP2 ( ) SS: (start/stop) SI: SP:

2 JP2 Connector 7 8 registers: ACC (Accumulator) IX (Index register) specific role ACC : used for input / output IX : Used for modification JP1 Connector byte 512 byte program area data area Instruction Code A register B Addressing Immediate 10- Absolute Address 11- Index Modification B 511 Instruction length is 8 bit / 16 bit each instruction specifies up to 2 operands (A, B)

3 register immediate absolute Ins. Code A 00 A register Ins. Code A 01 immediate Ins. Code A 10 1 B B register index Ins. Code A Register is specified as an operand Ins. Code A 00 B A B Absolute memory is specified as an operand Ins. Code A 10 A Reg_A Reg_B Reg_A Reg_A op Reg_B Reg_A MM[] Reg_A Reg_A op MM[] Immediate value is specified as an operand Ins. Code A 01 immediate value A Index modified memory is specified as an operand Ins. Code A 11 A Reg_A immediate Reg_A Reg_A op immediate Reg_A MM[IX + ] Reg_A Reg_A op MM[IX + ]

4 Add (1) 4 types of Add register ing Reg_A Reg_A+Reg_B absolute ing Reg_A Reg_A+MM[B] immediate ing Reg_A Reg_A+B index modification Reg_A Reg_A+MM[IX+B] ACC IX ADD register ing notation: ADD ACC, IX meaning: ACC ACC + IX ACC IX Add (2) Add (3) ADD ACC absolute ing ADD ACC immediate ing immediate value notation: ADD ACC, [80H] notation: ADD ACC, 3 meaning: ACC ACC+MM[80H] meaning: ACC ACC+3 ACC IX ACC IX Add(4) Load ADD ACC index modification notation: ADD ACC,[IX+80H] meaning: ACC ACC+MM[IX+80H] 4 types of Load register ing Reg_A Reg_B absolute ing Reg_A MM[B] immediate ing Reg_A B index modification Reg_A MM[IX+B] ACC IX

5 Load (1) Load (2) LD ACC IX notation: LD ACC, IX meaning: ACC IX LD ACC absolute ing notation: LD ACC, [80H] meaning: ACC MM[80H] ACC IX ACC IX Load (3) Load (4) LD ACC immediate ing immediate value LD ACC index modification notation: LD ACC, 3 notation: LD ACC,[IX+80H] meaning: ACC 3 meaning: ACC MM[IX+80H] ACC IX ACC IX (P0-P4) P0:, ++ P1:() P2-P4 P0 P1 P2 P3 P bit instruction MM Execute immediate branch shift Execute 16 bit instruction ++ MM Execute 29 See Figure 2 (P.5) for detail absolute index modification 30 5

6 (P0) (P1) Enternal CBUF (P2) (P3) (P4) EQU, END : D1: EQU 80H //define the of D1 D2: EQU 81H //define the of D2 ANS: EQU 82H //define the of ANS LD ACC, [D1] //ACC [D1] ADD ACC, [D2] //ACC ACC+[D2] ST ACC, [ANS] //[ANS] ACC HLT //halt END //end of program

7 Power connector connector select switch LD ACC, [A] A is a memory location of program area 0 ~ LD ACC absolute ing frequency LED In operation LED Single phase 7 segment LED Single instruction Normal phase Execution control switch Register select switch Address display LED LD ACC, (A) A is a memory location of data area 256 ~ 511 Data display LED LD ACC absolute ing Reset switch Data switch Write switch 38 AC AC ON OFF AC AC TA C,,,ACC,IX

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