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2 MICROPROCESSORS The 8086/8088, 80186/80286, 80386/80486 and the Pentium Family Nilesh B. Bahadure Reader Department of Electronics and Telecommunication Engineering Bhilai Institute of Technology, Durg PHI Learning Private Limited New Delhi

3 MICROPROCESSORS: The 8086/8088, 80186/80286, 80386/80486 and the Pentium Family Nilesh B. Bahadure 2010 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be reproduced in any form, by mimeograph or any other means, without permission in writing from the publisher. ISBN The export rights of this book are vested solely with the publisher. Published by Asoke K. Ghosh, PHI Learning Private Limited, M-97, Connaught Circus, New Delhi and Printed by Baba Barkha Nath Printers, Bahadurgarh, Haryana

4 To My Parents Smt. Kamal B. Bahadure and Shri Bhaskarrao M. Bahadure and to my wife Shilpa N. Bahadure

5 Contents Preface... xix 1. Introduction History of Computers Block Diagram of a Microcomputer Microprocessors: History and Information 3 1.4Intel Evolutions 5 2. Architecture and Functional Block Diagram of Microprocessor Features of 16-Bit HMOS Microprocessor Pin Configuration of Microprocessor Common Pins Minimum Mode Pins of Microprocessor Maximum Mode Pins of Microprocessor Architecture of Microprocessor General Purpose Registers Operand Register or Temporary Registers Arithmetic Logic Unit (ALU) Flag Registers Instruction Queue and Pipelining Segmentation of Memory Used with Methods of Generating Physical Address in Microprocessor v

6 vi Contents 2.7 Memory Pointers IP (Instruction Pointer) Register SP (Stack Pointer) Register BP (Base Pointer) Register BX (Base), SI (Source Index) and DI (Destination Index) registers Use of SI and DI in String Instruction Default and Specified Segment Registers of Memory Pointers Addressing Modes of Microprocessor bit Microprocessor Pin Configuration of 8088 Microprocessor Architecture of Microprocessor Differences between Microprocessor 8086 and Review Questions Instruction Sets and Programming of Microprocessor Introduction Data Transfer Instructions MOV D, S (Move Source Data into Destination) XCHG D, S (Exchange the Content of Destination and Source) LAHF (Load AH Register with 8 LSBs of Flag Register) SAHF (Store Register AH into 8 LSBs of Flag Register) LDS R, Mem [Load DS (Data Memory Segment) and Given Register R (16 bit Register) with Memory Contents] LES R, Mem [Load ES (Data Memory Segment) and Given Register R (16-bit Register) with Memory Contents] LEA R, EA Source (Load Effective Address of Memory into Given Register R) XLAT/XLATB (Translate/Translate Byte) Stack Instructions Initialization of Stack Memory Segment Saving Useful Data of Register into Stack Memory Location Transferring Back Data from Stack Memory Location to Corresponding Destination Instruction Used is POP D (16 bits) Input and Output Instructions IN AL/AX, 8-bit Port Address/DX OUT 8-bit Port Address/DX, AL/AX Arithmetic Instructions ADD D, S (Add Destination and Source Data) ADC D, S (Add Destination and Source Data with Carry) DAA AAA (ASCII Adjust after Addition) SUB D, S (Subtract Source Data from the Destination Data) 61

7 Contents vii SBB D, S (Subtract the Content of Source with Borrow from the Content of Destination) DAS (Decimal Adjust after Subtraction) AAS (ASCII Adjusts after Subtraction) CMP D, S (Compare Destination and Source Data) INC D (Increment the Content of Destination) DEC D (Decrement the Content of Destination) NEG D [Negate (Negative) Contents of Destination] CBW (Convert Sign Byte into Sign Word) CWD (Convert Sign Word into Sign Double Word) Multiplication Instructions Unsigned Number Multiplication Signed Number Multiplication Division Instructions Unsigned Number Division Signed Number Division Logical Instructions AND D, S (AND Destination and Source Data) TEST D, S (AND Destination and Source Data) OR D, S (OR Destination and Source Data) XOR D, S (XOR Destination and Source Data) ROL D, Count (Rotate Left Destination without Carry) RCL D, Count (Rotate Left Destination with Carry) ROR D, Count (Rotate Right Destination without Carry) RCR D, Count (Rotate Right Destination through Carry) SAL/SHL D, Count (Shift Arithmetic Left/Shift Logical Left Destination Data and Put Zeros in the LSBs) SHR D, Count (Shift Logical Right Destination Data and Put Zeros into MSBs) SAR D, Count (Shift Arithmetic Right Destination Data and Put MSBs Bit into MSBs Itself) NOT D (Note Destination Data) Flags Controlling Instructions STC (Set Carry Flag) STD (Set Direction Flag) STI (Set Interrupt Flag) CLC (Clear Carry Flag) CLD (Clear Direction Flag) CLI (Clear Interrupt Flag) CMC (Complements the Carry Flag) String Instructions REP (Unconditional Repeat) REPZ/REPE (Repeat if Result is Zero/Repeat if Equal) REPNZ/REPNE (Repeat if Result is not Zero/Repeat if not Equal) Loop Label 92

8 viii Contents LOOPZ/LOOPE LABEL (Loop If Result is Zero/Loop If Equal) LOOPNZ/LOOPNE LABEL (Loop If Result is not Zero/Loop If not Equal) MOVSB/MOVSW (Move String Byte/Move String Word) LODSB/LODSW (Load String Byte in Register AL or String Word into Register AX) STOSB/STOSW (Store String Byte or Store String Word) SCASB/SCASW (Scan a String Byte or a String Word) CMPSB/CMPSW (Compare String Byte or Compare String Word) Branching Instructions Addressing Modes of Branching Instructions Types of Branching Instructions External Syncronization and Machnine Control Instructions NOP (No Operation) HLT (Halt Processing) WAIT (Wait for Test Signal or Interrupt Signal) LOCK (Lock the Bus Signals) ESC (Escape) 121 Review Questions Assembly Language Programming of Microprocessor Introduction to the Programming Languages Machine Language or Low-level Language Hexadecimal Language Assembly Language High-level Language Assembler Directives or (Pseudoinstructions) DB (Define Byte) DW (Define Word) DD (Define Double Word) DQ (Define Quad Word) DT (Define Ten Bytes) ASSUME SEGMENT and ENDS ORG (Originate) END EQU Short, Near, Far LABEL LENGTH PROC and ENDP USES PTR EVEN or ALIGN2 134

9 Contents ix ALIGN PUBLIC and EXTRN OFFSET Programming 135 Review Questions Interrupts of Microprocessor Basics of Interrupts Software Interrupt of Microprocessor Vector Interrupt Table (VIT) or Interrupt Vector Table (IVT) Classification of INTn Instruction Hardware Interrupts of Microprocessor NMI INTR Differences between Software and Hardware Interrupt 160 Review Questions Memory Interfacing with Microprocessors 8086 and Semiconductor Memory Fundamentals Memory Types RAM Memory Types Standard EPROM ICs Standard SRAM ICs Standard DRAM ICs Memory Structure and Its Requirement Physical Structure of Practical Memory ICs Basic Concepts of Memory Interfacing Memory Decoding Absolute or Full Decoding Linear or Partial Decoding Supporting Circuits Used for the Interfacing Clock Generator Bus Controller Bus Arbiter Latch LS138 3-to-8 Line Decode/Demultiplexer Programmable Array Logic (PAL) or Programmable Logic Array (PLA) Available Programmable Arrays Logics (PALs) Memory Mapping with Microprocessor Memory Mapping with Microprocessor Review Questions 219

10 x Contents 7. Timing Diagram of Microprocessor Minimum and Maximum Modes of Operation Bus Operation I/O Addressing ALE (Address Latch Enable) Timing Diagram of Opcode Fetch, Memory/IO Read, Memory/IO Write in Minimum and Maximum Modes Timing Diagram or Bus Cycle or Machine Cycle of Read (Memory/IO) of Minimum Mode (or) Opcode Fetch/Memory Read/IO Read Machine Cycle of 8086 in Minimum Mode Timing Diagram or Bus Cycle or Machnine Cycle of Read (Memory/IO) of Minimum Mode with One Wait State Opcode Fetch/Memory Read/IO Read Machine Cycle of 8086 in Maximum Mode Memory Write/IO Write Machine Cycle of 8086 in Minimum Mode Memory Write/IO Write Machine Cycle of 8086 in Minimum Mode with One Wait State Memory/IO Write Machine Cycle of 8086 in Maximum Mode Bus Write Cycle (Memory or I/O) Interrupt Acknowledge Machine Cycle 231 Review Questions Numeric Data Processor Features of 8087 Math Coprocessor Architecture of 8087 Math Coprocessor Pin Configuration of 8087 Math Coprocessor Status Register of 8087 Math Coprocessor Tag Word Register of 8087 Coprocessor Control Register of 8087 Math Coprocessor Interfacing of 8087 Coprocessor with 8086/8088 Microprocessor Synchronization or Cooperation of Coprocessor 8087 with Main Host Processor 8086/ Program Execution of 8086 and Data Transfer between 8087 and Memory Operation of Coprocessor when Request Signal RQ is Given by Some Other Local Bus Master Operation of Busy and Test Pins or Wait Operation Instruction Sets of 8087 Coprocessor Data Transfer Instructions Constant Data Transfer Instruction Arithmetic Instructions Comparison Instruction Transcendental Instructions Processor Control Instructions 256

ISBN : 97881203394 22 Author : BAHADURE, NILESH B.

11 Microprocessors : The 8086/8088,80186/80286,80386/80486 And The Pentium Family 25% OFF Publisher : PHI Learning ISBN : Author : BAHADURE, NILESH B. Type the URL : Get this ebook

3.1 DATA MOVEMENT INSTRUCTIONS 45

3.1.1 General-Purpose Data Movement s 45 3.1.2 Stack Manipulation... 46 3.1.3 Type Conversion... 48 3.2.1 Addition and Subtraction... 51 3.1 DATA MOVEMENT INSTRUCTIONS 45 MOV (Move) transfers a byte, word,