Case study of IBIS V4.1 by JEITA EDA-WG
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1 Case study of IBIS V4.1 by JEITA EDA-WG June 8, 2004 IBIS SUMMIT in San Diego, California JEITA EDA-WG A. Itoh,, T. Watanabe, N. Matsui JEITA ; Japan Electronics and Information Technology Industries Association JEITA All Rights Reserved. 1
2 Outlines 1. JEITA EDA-WG Activities 2. Case study of IBIS V EMI Model JEITA All Rights Reserved. 2
3 1. JEITA EDA-WG Activities JEITA All Rights Reserved. 3
4 EDA Model for Objectives of JEITA EDA Digital Consumer Electronics Cellular Phone, LCD TV, Digital Camera/Video, DVD Recorder (Digital, RF, and Analog circuits) Auto Mobile Electronics? (Motor Drive, EMC) < Applicability of IBIS V4.1 > JEITA All Rights Reserved. 4
5 EDA Model for SI, PI and EMI Simulation PCB FPC Cables Connectors Passive Component (LCR, Filter) RF Modules LSI Model IC Chip IC Package Display device Discreet Semicon Crystal Oscillator JEITA All Rights Reserved. 5
6 IC Package ICs RF Modules Passive Components (LCR, Filter) Discrete Semiconductors Crystal Oscillator EDA Models For Digital Consumer electronics Connectors Cables FPC PCB JEITA All Rights Reserved. 6
7 JEITA EDA-WG Member Digital Consumer Electronics Supplier Discrete ICs Panasonic Sony Sharp Canon Toshiba Shin Dengen EDA(internal/vendor) Fujitsu Mitsubishi Apsim Semicon NECEL Toshiba EDA Models For Digital Consumer electronics Connectors JAE FPC JEITA All Rights Reserved. Mectron Passive Components TDK Murata PCB CMK 7
8 2. Case study of IBIS V4.1 JEITA All Rights Reserved. 8
9 Summary of investigation of IBIS V4.1 ASIC/SOC for EMI/SSO Power Semiconductor OpAMP DSP, AD/DA, Xtal Passive Components Package, Module, PCB Connector, Cable, FPC V3.2 ( ) ( ) IBIS V4.1 SPICE V4.1 *AMS ( ) ( ) (?) ICM Comments Accurate models need the internal gates for EMI/SSO. IBIS V4.1 SPICE discloses process parameters. IBIS V4.1 SPICE discloses process parameters. I/O for SI can be described in V3.2. Inside needs *AMS. Can describe LCRK models ICM describes S-parameters (?) IBIS 4.1 SPICE can t describe ( ) ( ) JEITA All Rights Reserved. S-parameters or lossy coupled transmission line. ICM can t include discrete components. SiP and PWRGND modeling. ICM can t include discrete components. 9
10 Understanding of IBIS V4.1 ICM V1.0 IBISV4.1 [Component] [Node Declarations] [Circuit Call] VHDL-AMS SPICE3 Verilog-AMS IBIS [Model] Model_type [External Model] [External Circuit] IMIC (Table_SPICE) IBIS excludes IMIC JEITA All Rights Reserved. 10
11 How to describe SPICE transistor model in in IBIS 4.1 without disclosing proprietary information Models described in SPICE transistors have flexibility. Net List Equivalent Circuit (Macro Model) using Transistor Models Transistor Parameters IBIS V4.1 allows to use SPICE3 but discloses process parameters IMIC (Table_SPICE) allows to hide the transistor parameters, but IBIS V4.1 excludes IMIC. JEITA All Rights Reserved. 11
12 How to hide transistor model parameters in in IBIS V4.1 SPICE description without losing accuracy IMIC (Table_SPICE) allows to hide the transistor parameters, but IBIS V4.1 excludes IMIC. Need to have a bridge from IMIC to IBIS V4.1 SPICE 3 without disclosing the original SPICE transistor parameters. JEITA All Rights Reserved. 12
13 3. EMI Model (NEC/APSIM) NEC/APSIM All Rights Reserved. 13
14 LSI Model for EMI Simulation LSI Power Supply RF Current of LSI 1. Measurement; IEC Magnetic Probe Method 2. Simulation Model; EMI Model for LSI NEC/APSIM All Rights Reserved. 14
15 EMI Simulation for PCB LSI PCB Chip power RF Current IO Model Power and Ground Model input PCB PKG PKG Clock output ground Power/Ground Plane Power/Ground Plane Input/ Output Clock Macro Non-Clock Macro EMI simulation needs the internal gates power/ground model with loading effects in time/frequency domain. NEC/APSIM All Rights Reserved. 15
16 Current Waveforms of 32-bit LSI Output Internal Total NEC/APSIM All Rights Reserved. 16
17 Measurement IEC Magnetic Probe Method Spectrum analyzer Pre-amplifier (option) Magnetic probe LSI Magnetic field IC test board Current Decoupling capacitor NEC/APSIM All Rights Reserved. Power supply 17
18 Simulation VS Measurement dbua 8Tr D,FL,RAM Simulation Measurement 5s(D) 5s(B+D+F) 実測 MHz NEC/APSIM All Rights Reserved. 18
19 Current/Magnetic Field Distribution Simulation Measurement APSIM NEC/APSIM All Rights Reserved. 19
20 EMI Simulation Model for LSI Power and Ground Model of Core Logics (internal gates) PKG PKG power RF Current input output Input Clock Macro Non-Clock Macro Output ground IBISV3.2 IMIC IBISV3.2 IBIS 4.1 NEC/APSIM All Rights Reserved. 20
21 Developed IMIC to IBIS V4.1 Converter Any SPICE.MODEL Any SPICE Table_SPICE Generator Table_SPICE.MODEL IMIC Table_SPICE to SPICE 3 MODEL3 Converter SPICE 3 LEVEL=3.MODEL IBIS V4.1 The parameters of LEVEL=3 can t disclose those of the original SPICE. NEC/APSIM All Rights Reserved. 21
22 Full chip power/ground current models in in time/frequency domain for EMI Simulation Table LEVEL=3 NEC/APSIM All Rights Reserved. 22
23 Example of LSI Power/Ground Model (IBIS V 4.1) NEC/APSIM All Rights Reserved. 23
24 1 Example of LSI Power/Ground Model (IBIS V 4.1) Original SPICE MOS parameters 2 Table_SPICE MOS V-I-C data 3 SPICE 3 Level=3 MOS minimum parameters NEC/APSIM All Rights Reserved. 24
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