Japanese two Samurai semiconductor ventures succeeded in near 3D-IC but failed the business, why? and what's left?

Transcription

1 Japanese two Samurai semiconductor ventures succeeded in near 3D-IC but failed the business, why? and what's left? Liquid Design Systems, Inc CEO Naoya Tohyama

2 Overview of this presentation Those slides shows many technology information of 2 venture companies, however, the presentation will more focus on business results of 2 companies to refer why they did not make success with advanced semiconductor technologies with big motivation (Samurai mind) such as innovating LSI architecture. Business slides will be shown at the forum. I will see you there..

3 Background of 2 semiconductor ventures System Fabrication technologies founded in The company developed new chip architecture, called System in silicon. The company spent US$19 for 5 years to complete the first production. The company went bankrupt in not to maintain the venture capital. TAG founded in The company developed new chip architecture, called PerfectSoC. The company spent several US$ for 5 years to complete the first production. The project terminated in Both companies technologies succeed by SFT sold patents to LDS (founded by 2 ex-sft employees) TAG sold patents to Vintasys (founded by 1 ex-tag employee) Both technologies focus on 2.5 to 3D IC. And both still keep Samurai sprits to put these technologies out to the world.

4 Index Seeds and needs Introduction of SiS technologies Patents Future technology concept Our business model

5 Issues of Digital System BUS Bottle neck Increasing SRAM for date transfer Ultra High Density SRAM SRAM SRAM Bus line ASIC DRAM SRAM SRAM LOGIC Design issues High Power Noise Timing Overhead (Redundancy,BIST) Layout timing

6 Target market of new chip when development started Memory Capacity (Mbit) 1G SIP with generic DRAM edram SoC Bus width NG (~32bit) OK Capacity OK(16M~1G) NG(~64M) Power NG OK Time to market OK NG 512 Cost (NRE) OK NG SIP with generic DRAM Customer Requirement (New Chip architecture) ASIC pin-count NG (Bonding limit) OK 32 edram SoC Bandwidth (GB/s)

7 Recent trend of high-end application High speed bus Design difficulty of DDR with expensive patent cost Larger embedded memory capacity (more than 256Mbit) TSV(Through Silicon Via) Takes another 2 years for mass production cost level Many players now participate Japan: Toshiba, Renesas, Elpida/ Qimonda, Zycube, W/Wl: IBM, Samsung, Fraunhofer, ITRI, IME, CEA-LETI, Silicon interposer DNP Shinko Renesas (Resin interposer) And more player are coming

8 Index Seeds and needs Introduction of SiS technologies Patents Future technology concept Our business model

9 ISSCC-2006 San Francisco) (Technology & Architecture Direction: 23.7 ) System-in-Silicon Architecture and its Application to H.264/AVC Motion Estimation for 1080HDTV SiSRAM (64Mb) RAM I/O SiIP SiSRAM (64Mb) RAM I/O Interface Macro Interface Macro ASIC (TSMC 0.18μm) PLL Flip mount 64Mb SiSRAM Area 64Mb SiSRAM Area RAM I/O SiSRAM Chip Interface Macro Interface Macro ASIC Area SiIP Die Flip mount ASIC Chip

10 Conventional packaging with SiS Architecture Micro-bumps for the high density connection 10% Lower thermal resistance compared to conventional SoC Using & improving existing EDA and manufacture equipment ASIC SiS-RAM Micro Bump SiIP (Silicon Interposer)

11 Structure of SIS image image package Micro-bumps connecting between ASIC and SISRAM(memory) Si interposer Si interposer SISRAM SISRAM interposer Bonding wire IFマクロ IOバッファ ASIC ASIC PAD Stitch IF macro ASIC

12 SIS & SiIP TSV PKG test chip - bird s View (ECTC2008@Orland, 3D and Through Silicon Via: 13.6) t = 1.11mm Mold 11.0mm SiIP Bonding Wire Organic print board (2-layer) Outer Ball 50μm SiIP + BGA (Ref.) SiIP TSV PKG Test Chip Si interposer=200um t 0.42mm

13 Fabrication of System-in-Silicon R Flip mount 128Mb SiSRAM Area 128Mb SiSRAM Area DRAM I/O SiSRAM Chip Interface Macro Interface Macro ASIC Area ASIC Chip SiIP Die Flip mount

14 Compare with DDR - Same Bandwidth DDR Power consumption of memory DDR2-533 DDR2-533 DDR2-533 DDR ASIC 64 x 533MHz = 4.2GB/s EMI Hard Timing Terminal Resistance Rambus Patent SiS 1Chip solution Easy Timing Low power Reduce pin count SISRAM 64M nm ASIC Same Bandwidth 512 x 66MHz = 4.2GB/s System-in-Silicon ~ 4W Power < 1/8 ~500mW ~ Fan ~ no FAN

15 Compare with DDR - Wider Bandwidth DDR Power consumption of memory DDR2-800 DDR2-800 DDR2-800 DDR ASIC 64 x 800MHz = 6.4GB/s EMI Hard Timing Terminal Resistance Rambus Patent Wider Bandwidth > 4W 消費電力 < 1/4 ~ Fan SiS 1Chip solution Easy Timing Low power Reduce pin count SISRAM 128M 512 SISRAM 128M nm ASIC 1024 x 66MHz = 8.4GB/s System-in-Silicon ~1W ~ no FAN

16 Comparison of Power consumption Memory Type Data Rate Power for VDD Power for Interface Total Power consumption MobileDDR333 (x32:167mhz) 2 pieces 333Mx32x2/8=2.67GB/s P=150mAx2x P=20pFx64x1.2Vx1.2V/6ns CL(I/O)=20pF Ptotal= = 693.6mW 256MSISRAM (x256:100mhz)1 piece 100Mx256/8=3. 2GB/s P=100mAx1.2V= P=1.5pFx256x1.2Vx1.2V/2 CL(D/Q)=1.5pF Ptotal= = 133.9mW 512MSISRAM (x512:100mhz)1 piece 100Mx512/8=6. 4GB/s P=100mAx1.2Vx P=1.5pFx512x1.2Vx1.2V/2 CL(D/Q)=1.5pF Ptotal= = 267.7mW

17 Target and Market Capacity 1G DDR2/DDR3 512M 256M TV application 256M-SISRAM 25mm2 / 133MHz Target for 3D mobile Graphics 512M-SISRAM 50mm2 / 133MHz 128M-SISRAM x2 90mm2 128M 128M-SISRAM 45mm2 65nm edram 64M-SISRAM x2 70mm2 64M 64M-SISRAM 35mm2 90nm edram Bandwidth [GB/sec]

18 Last business after bankrupt (2008, March) HD camera module for cell phone (Korea) Low power 1/10 for memory Car navigation system (Domestic) Strong request for development 4G communication LSI(FPGA:major players) SIS with TSV:2010 target FPGA SISRAM TSV-Si interposer Built-up substrate (2-3 layers)

19 Index Seeds and needs Introduction of SiS technologies Patents Future technology concept Our business model

20 Technology Patents Existing in Japan 6 Under Examination 9 Abroad PCT 3 Taiwan 2 (Under examination) Score(3 rd organization evaluation) IPB patent score:rating A+ ~ A-

21 Technologies field SIS structure Interposer structure Micro bump structure SISRAM(memory) circuit DRAM circuit to enwide bandwidth Test micro bump test SISRAM(memory) circuit test

22 Index Seeds and needs Introduction of SiS technologies Patents Future technology concept Our business model

23 3D SiS with TSV(Through Silicon Via) ASIC Heat Spreader SISRAM Pierced electrode Silicon Interposer

24 SISRAM Stack structure SiS = Encapsulated active layers High thermal conduction through μ-bumps BGA with TSV High terminal density VG supply improvement (Bottom view) Solder bumps (~150um) Stackable DRAM w/ bank architecture Memory Stack w/ Wafer-on-Wafer Tech. (for large bit capacity ~4Gbit) DRAM ASIC DRAM BANK0 BANK2 BANK1 BANK3 Improvement of the data transfer rate >DDR DIMM Dual Channel ~30GBps with Random burst Micro bump (~20um) Cost down of Silicon Interposer Reduction of outer balls Hard IP lineups: FLASH / High speed IO / Voltage regulator Platform

25 PerfectSoC TM structure 3D IntegrationIn Pckage by Vintasys Corp. Memory Dummy CPU System IntegrationOn Silicon(PerfectSoC TM ) + Burn-In TEST C R Tr Di PWR RGB Dr Audio MemoryVeri.Engine System Veri. Engine Large C R w/ High accuracy Shotky Di for RF Integrated Passive In PCB Large L Source: Vintasys Corp.

26 Market Needs and Contemporary Solutions Whole system requires High Speed Low Power Robustness High Reliability System Compaction Contemporary Solutions are SoC (System on Chip) SiP (System in Package) Source: Vintasys Corp.

27 What is PerfectSoC TM? Needs from market CPU Bare Chip DSP Bare Chip SDRAM Bare chip Embedded By pass Capacitors Embedded Logic circuits Embedded Analog Circuits Optimized Transmission Line Embedded Discrete Circuits Embedded Memory Test Engines Embedded System Verification Engine Integration on Silicon PerfectSoC TM Solution Integrate the system components as many as possible into mature CMOS and/or Bipolar semiconductor Source: Vintasys Corp.

28 PerfectSoC TM Example Graphic Eng. Platform SDRAM ASIC PerfectSoC Dummy SDRAM Organic Interposer Cross Section Top View w/o Mold Source: Vintasys Corp.

29 Index Seeds and needs Introduction of SiS technologies Patents Future technology concept Our business model

30 Will be shown in the presentation SAMURAI project among Taiwan and Japan Semiconductor Asset Multiple Reuse by Advanced IPs.

31 Contact us Naoya Tohyama C.E.O. Liquid Design Systems, Inc. Address: KSP 421B, Kawasaki-city, Kanagawa, Japan Phone: Facsimile: