Functional Differences Between the DSP56311 and DSP56321

Transcription

1 Freescale Semiconducor Engineering Bullein EB365 Rev 5, 10/2005 Funcional Differences Beween he DSP56311 and DSP56321 The DSP56311 and DSP56321, wo members of he Freescale DSP56300 family of programmable digial signal processors (DSPs), suppor nework applicaions wih general filering operaions Like oher DSP56300 family members, hese devices preserve code compaibiliy Unique o each of hese devices is an on-chip enhanced filer coprocessor (EFCOP) ha execues filer algorihms in parallel wih core operaions o provide enhanced signal qualiy wihou affecing channel hroughpu or oal number of channels suppored, resuling in increased performance overall Alhough he DSP56311 and DSP56321 have similar feaures, hey differ in several ways This documen describes hese funcional differences 1 Migraion Consideraions CONTENTS 1 Migraion Consideraions 1 2 Summary of Differences 2 3 Volage 3 4 Operaing Frequency 3 5 Pin Definiions 3 6 Thermal Characerisics 4 7 ID Regisers 4 8 Inernal Memory Size 4 9 Memory Mapping 7 10 EFCOP/Core Shared Memory S Access Wai Saes D Suppor Operaing Mode Regiser Clock/PLL PLL/DPLL Conrol Regisers Peripheral Timing Package 19 The DSP56311 uses he Freescale HiP4 process The DSP56321 uses he laes Freescale process echnology: HiP7 The migraion from he HiP4 o he HiP7 process decreases he core volage; increases he maximum operaing frequency; and changes specific pin definiions, he chip hermal characerisics, he JTAG and Device Idenificaion regiser conens, inernal memory size, memory mapping, shared EFCOP/core memory size, S and D access, Operaing Mode Regiser (OMR) bi definiions, clock/phaselock loop (PLL) module o a DPLL circui wih differen Freescale Semiconducor, Inc, 2001, 2005 All righs reserved

2 Summary of Differences configuraion regisers, and packaging The following secions address he hardware and sofware implicaions for migraing DSP56311 designs o DSP56321 designs 1RWH 0LQRUFKDQJHVDUHUHTXLUHGIRUFRUUHFWV\VWHPRSHUDWLRQLID'63LVVXEVWLWXWHGIRUD '63LQDGHVLJQ)UHHVFDOHGRHVQRWJXDUDQWHHFRUUHFWRSHUDWLRQLI\RXGRQRWLPSOHPHQWWKH UHTXLUHGGHVLJQFKDQJHVGHVFULEHGLQWKLVGRFXPHQW 2 Summary of Differences Table 1 summarizes he differences beween he DSP56311 and he DSP56321 and references he secions of his documen ha describe he differences in deail Feaure See Secion Table 1 Differences Beween DSP56311 and DSP56321 DSP56311 DSP56321 Volage 3 18 V ± 01 V (separae core and PLL) 16 V ± 01 V (shared core and DPLL) Targe operaing MHz 275 MHz frequency Pin definiion differences Thermal characerisics 5 V CCP, V CCP1, and GND P are power and ground dedicaed for PLL use PCAP connecs o special PLL capacior CAS, RAS, BCLK, BLCK, and CLKOUT used o suppor D and Address Trace Mode ( 100 MHz only) 6 θ JA = 49 C/W θ JC = 10 C/W ID regisers 7 Device ID (IDR) = $ JTAG ID = $0180B01D Core and DPLL use he same power and ground supplies The old V CCP pin is used as a V CCQL connecion The old GND P and GND P1 pins are used as GND Q connecions, bu are simply designaed as GND for he chip pinou because all GND connecions mus be conneced ogeher PCAP is no conneced (NC) CAS, RAS, BCLK, BCLK, and CLKOUT funcions are no suppored R θja = 44 C/W R θjc = 7 C/W The daa shee also specifies new values: R θjma : 2s2p, Naural = 25 C/W 1s, 200 f/min air flow = 35 C/W 2s2p, 200 f/min air flow = 22 C/W R θjb = 13 C/W Device ID (IDR) = $ JTAG ID = $ D Inernal memory K 24-bi on-chip S 192 K 24-bi on-chip S Memory maps 9 Memory map includes five swich opions (including defaul) EFCOP/Core shared memory S access wai saes K 24-bi 12 K 24-bi 11 Accesses a 100 MHz or less require a leas 1 wai sae Accesses above 100 MHz o 150 MHz require a leas 2 wai saes Programming he Bus Conrol Regiser for 2 7 wai saes adds 1 railing wai sae Selecing 8 or more wai saes adds 2 railing wai saes Memory map includes eigh swich opions (including defaul) Accesses a 275 MHz require a minimum of 3 wai saes Programming he Bus Conrol Regiser for 3 7 wai saes adds 1 railing wai sae Selecing 8 or more wai saes adds 2 railing wai saes D suppor 12 D is suppored o 100 MHz D is no suppored Operaing Mode Regiser (OMR) 13 Bis 22 and 21 are MSW[1 0], bi 7 is MS Bis 22,21,7 are MSW[2 0] o increase he number of swich opions; bi 15 (Address Trace Enable) is undefined 2 Freescale Semiconducor

3 Volage Table 1 Differences Beween DSP56311 and DSP56321 (Coninued) Feaure See Secion DSP56311 DSP56321 Clock/PLL 14, 15 Sandard DSP56300 PLL and nonsynhesized clock block Peripheral iming 16 Based on 150 MHz Timing expressions use HiP4 delay consans Package mm 15 mm 196-pin Molded Array Process-Ball Grid Array (MAP-BGA) DPLL (wihou PCAP) and a new synhesized, scannable, clock block Based on 275 MHz Timing expressions use HiP7 delay consans 15 mm 15 mm 196-pin Flip Chip-Plasic Ball Grid Array (FC-PBGA) 3 Volage The DSP56311 and DSP56321 are dual-volage devices The DSP56311 core operaes from a 18 ± 01 V supply, while he DSP56321 core and DPLL operae from a 16 ± 01 V supply The inpu/oupu pins on each device operae from an independen 33 V supply Using a variable supply for he core volage allows designers o use he same board design for eiher device 4 Operaing Frequency The maximum operaing frequency for he DSP56311 is 150 MHz compared o 275 MHz for he DSP Pin Definiions Due o he change from he sandard DSP56300 phase-lock loop (PLL) design o he new digial phase-lock loop (DPLL) and clock block on he DSP56321, he PCAP pin is no longer necessary and he DSP56321 does no require a separae PLL power source The PCAP connecion is changed o NC V CCP connecs o he core power V CCQL and GND P and GND P1 connec o sysem GND Since D suppor and Address Trace Mode are no included in he DSP56321, he CAS, BCLK, BCLK, and CLKOUT signals are no suppored CAS and BCLK are disconneced inernally (NC) BCLK and CLKOUT are Reserved The RAS[0 3] funcions are also no suppored The DSP56321 Technical Daa shee provides deails on he chip pin-ou Table 2 Pin Differences Beween he DSP56311 and DSP56321 Signal Package Reference Number DSP56311 DSP56321 M6 V CCP V CCQL M9 CLKOUT Reserved 1 M10 BCLK NC 2 N6 GND P GND N7 AA3/RAS3 AA3 N8 CAS NC 2 N10 BCLK Reserved 1 N13 AA0/RAS0 AA0 P5 PCAP NC 2 P6 GND P1 GND P7 AA2/RAS2 AA2 P12 AA1/RAS1 AA1 Freescale Semiconducor 3

4 Thermal Characerisics Table 2 Pin Differences Beween he DSP56311 and DSP56321 (Coninued) Signal Package Reference Number DSP56311 DSP56321 Noes: 1 These pins are conneced inernally and are reserved Legacy designs wih connecions for CLKOUT or BCLK can remain unchanged, bu suppor for CLKOUT and BCLK is no guaraneed a any frequency 2 These pins are no conneced inernally No connecion modificaions o legacy designs are required for correc operaion 6 Thermal Characerisics Table 3 Summary of Differences Beween he 196-Pin MAP-BGA and FC-PBGA Packages Characerisic DSP56311 DSP56321 Θ JA ( C/W) 49 (no airflow) 50 (no airflow) simulaed Acual daa TBD Θ Jc ( C/W) simulaed Acual daa TBD 7 ID Regisers The DSP56300 core provides a dedicaed user-accessible es access por (TAP) based on he IEEE Sandard Tes Access Por and Boundary Scan Archiecure Wih he IDCODE insrucion, a user can deermine from he TAP ID Regiser informaion abou he manufacurer, par number, and version of a board componen The ID regiser is updaed o reflec informaion specific o he DSP56321 Figure 1 shows he specified regiser conens for he DSP56311 and DSP56321 Device 31 Version Informaion Design Cener Number The device Idenificaion Regiser (IDR) is a 24-bi, read-only facory-programmed regiser ha idenifies DSP56300 family members I specifies he derivaive number and revision number of he device This informaion is used in esing or by sofware The IDR is updaed o reflec informaion specific o he DSP56321 Figure 2 shows he specified regiser conens for he DSP56311 and DSP Sequence Number Manufacurer Ideniy DSP DSP Figure 1 JTAG Idenificaion Regiser Conens for DSP56311 and DSP Device Reserved Revision Number Derivaive Number DSP56311 $00 $0 $311 DSP56321 $00 $0 $321 Figure 2 Idenificaion Regiser Conens for DSP56311 and DSP Inernal Memory Size The DSP56311 has a oal of 128 K 24-bi on-chip S compared o a oal of 192 K 24-bi on-chip S in he DSP56321 In boh devices, S is pariioned ino program memory space (P), and wo daa memory spaces (X and Y) The program memory space (P) includes inernal Program, an opional inernal Insrucion Cache 1, a boo program ROM, and an opional off-chip memory expansion The daa memory space is divided ino 4 Freescale Semiconducor

5 Inernal Memory Size X- and Y-daa memory in order o work wih he wo address arihmeic logic unis (ALUs) and o feed wo operands simulaneously o he daa ALU Each daa memory space includes inernal and an opional offchip memory expansion The X- and Y-daa memory share a 10 K word memory block wih he EFCOP in he DSP56311 (20 K words oal) and a 12 K word memory block in he DSP56321 (24 K words oal) Figure 3 shows he defaul memory block diagram for he DSP56311 Figure 4 shows he defaul memory block diagram for he DSP56321 Memory Expansion Area Program 32 K 24 or (Program 31 K 24 and Insrucion Cache ) X Daa 48 K 24 Y Daa 48 K 24 Figure 3 DSP56311 Defaul Memory Block Diagram Memory Expansion Area Program 32 K 24 or (Program 31 K 24 and Insrucion Cache ) X Daa 80 K 24 Y Daa 80 K 24 Figure 4 DSP56321 Defaul Memory Block Diagram The amoun of inernal pariioned beween program and daa depends on he values wrien o four bis: Cache Enable bi (CE) in he Saus Regiser When he CE bi is se, he Insrucion Cache is enabled and he lowes 1K of inernal Program is reserved as Insrucion Cache When he cache is enabled, he address range is swiched o address exernal memory and he inernal memory area becomes inaccessible Memory Swich Mode bis (MSW[2 0] OMR[22, 21, and 7])The DSP56311 uses he MS bi (OMR[7]) o selec Memory Swich Mode and he MSW[1 0] bis (OMR[22 21) o selec he alernae memory maps when he mode is seleced; his resuls in five selecions: one defaul seing and four alernae seings In he DSP56321, he Operaing Mode Regiser (OMR) is redefined so ha he same hree bis (OMR[22, 21, 7]) make up a 3-bi Memory Swich Mode regiser If all hree bis 1 When he cache is disabled, he memory space used for he Insrucion Cache becomes available as inernal program When he cache is enabled, he on-chip cache memory space is inaccessible and he address range for his space is assigned o exernal program memory Freescale Semiconducor 5

6 Inernal Memory Size are zero, he defaul mode is seleced When any MSW bi is se, he Memory Swich Mode is enabled, and porions of he inernal X and Y daa memory become par of he on-chip inernal Program The amoun of X and Y daa memory ha becomes par of Program depends on he MSW bis, he Memory Swich Configuraion bis (MSW[2 0], bis 22,21, and 7 in he Operaing Mode Regiser) The MSW bis define eigh differen X and Y daa memory and inernal Program configuraions, including he defaul configuraion Table 4 (DSP56311) and Table 5 (DSP56321) show pariioning of on-chip in he DSP56311 and DSP56321 relaive o hese bi seings Program Size Insrucion Cache Size Table 4 DSP56311 Swich Memory Configuraion X Daa Size* Y Daa Size* Insrucion Cache (CE) Swich Mode (MS) MSW1 32 K 24-bi 0 48 K 24-bi 48 K 24-bi disabled disabled 0/1 0/1 31 K 24-bi bi 48 K 24-bi 48 K 24-bi enabled disabled 0/1 0/1 96 K 24-bi 0 16 K 24-bi 16 K 24-bi disabled enabled K 24-bi bi 16 K 24-bi 16 K 24-bi enabled enabled K 24-bi 0 24 K 24-bi 24 K 24-bi disabled enabled K 24-bi bi 24 K 24-bi 24 K 24-bi enabled enabled K 24-bi 0 32 K 24-bi 32 K 24-bi disabled enabled K 24-bi bi 32 K 24-bi 32 K 24-bi enabled enabled K 24-bi 0 40 K 24-bi 40 K 24-bi disabled enabled K 24-bi bi 40 K 24-bi 40 K 24-bi enabled enabled 1 1 *Includes 10 K 24-bi shared memory (ha is, memory shared by he DSP56300 core and he EFCOP) MSW0 Program Size Insrucion Cache Size Table 5 DSP56321 Swich Memory Configuraion X Daa Size* Y Daa Size* Insrucion Cache (CE) MSW2 MSW1 MSW0 32 K 24-bi 0 80 K 24-bi 80 K 24-bi disabled K 24-bi bi 80 K 24-bi 80 K 24-bi enabled K 24-bi 0 76 K 24-bi 76 K 24-bi disabled K 24-bi bi 76 K 24-bi 76 K 24-bi enabled K 24-bi 0 72 K 24-bi 72 K 24-bi disabled K 24-bi bi 72 K 24-bi 72 K 24-bi enabled K 24-bi 0 64 K 24-bi 64 K 24-bi disabled K 24-bi bi 64 K 24-bi 64 K 24-bi enabled K 24-bi 0 60 K 24-bi 60 K 24-bi disabled K 24-bi bi 60 K 24-bi 60 K 24-bi enabled K 24-bi 0 56 K 24-bi 56 K 24-bi disabled K 24-bi bi 56 K 24-bi 56 K 24-bi enabled K 24-bi 0 48 K 24-bi 48 K 24-bi disabled K 24-bi bi 48 K 24-bi 48 K 24-bi enabled K 24-bi 0 40 K 24-bi 40 K 24-bi disabled K 24-bi bi 40 K 24-bi 40 K 24-bi enabled *Includes 12 K 24-bi shared memory (ha is, memory shared by he DSP56300 core and he EFCOP) 6 Freescale Semiconducor

7 Memory Mapping 9 Memory Mapping Figure 5 shows a memory map configuraion of program memory swiching for he DSP56311 Figure 6 shows a memory map configuraion of program memory swiching for he DSP56321 Figure 5 DSP56311 Program Memory Swiching Configuraion Exernal Exernal Exernal Exernal 32K Exernal Inernal CE=0 32K Exernal Inernal 96K 48K Reserved Inernal 96K 64K Reserved Inernal 96K Reserved 96K 80K Inernal Inernal 1K Exernal 1K In Ex 1K In Ex 1K In Ex 1K In Ex CE=1 CE= 0 CE= 1 CE= 0 CE= 1 CE= 0 CE= 1 CE= 0 CE= 1 MS=0 MSW=00 Defaul MS=0 MSW=00 MS=1 MSW=11 MS=1 MSW=10 MS=1 MSW=01 MS=1 MSW=00 Figure 6 DSP56321 Program Memory Swiching Configuraion Ex Ex Ex Ex Ex Ex Ex Ex 112 K Res 112 K Res 112 K Res 112 K 72K Res 112 K 80K Res 112 K 96K Res 112 K In 64K 32K In 40K In 48K In In In In In 1K I n E x 1K I n E x 1K I n E x 1K I n E x CE = 0 1 CE = 0 1 CE = 0 1 CE = 0 1 CE = 0 1 CE = 0 1 CE = 0 1 CE = 0 1 1K I n E x 1K I n E x 1K I n E x 1K I n E x MSW=000 Defaul MSW=001 MSW=010 MSW=011 MSW=100 MSW=101 MSW=110 MSW=111 Freescale Semiconducor 7

8 Memory Mapping Figure 7 shows a memory map configuraion of X and Y daa memory swiching for he DSP56311 Figure 8 shows a memory map configuraion of X and Y daa memory swiching for he DSP56321 Figure 7 DSP56311 X and Y Daa Memory Swiching Configuraion Exernal Exernal Exernal Exernal Exernal 48K Inernal 48K Reserved 48K 40K Inernal 32K Reserved Inernal 48K 24K Reserved 48K 16K Reserved Inernal Inernal 10 K Shared 10 K Shared 10 K Shared 10 K Shared 10 K Shared MS=0 MSW=00 Defaul MS=1 MSW=11 MS=1 MSW=10 MS=1 MSW=01 MS=1 MSW=00 Figure 8 DSP56321 X and Y Memory Swiching Configuraion Ex Ex Ex Ex Ex Ex Ex Ex 80K In 80K Res 80K Res 80K Res 80K Res 80K 76K 72K 64K Res 80K Res 80K Res 60K In In In In 56K In 48K In 40K In 12 K Shar ed 12 K Shar ed 12 K Shar ed 12 K Shar ed 12 K Shar ed 12 K Shar ed 12 K Shar ed 12 K Shar ed MSW=000 Defaul MSW=001 MSW=010 MSW=011 MSW=100 MSW=101 MSW=110 MSW=111 8 Freescale Semiconducor

9 Memory Mapping Sixeen-bi Compaibiliy mode also affecs he memory configuraion for hese devices Figure 9 and Figure 10 show he effec of Sixeen-bi Compaibiliy mode on he memory map PROG X DATA Y DATA $FFFFFF INTERNAL $FFFFFF $FFFF80 (128 words) $FFFFFF $FFFFC0 $FFFF80 I/O $FF00C0 $FF0000 BOOTSTRAP ROM (192 words) $FFF000 $FF0000 INTERNAL $FFF000 $FF0000 INTERNAL $00C000 $00C000 $ K INTERNAL P 48K INTERNAL 48K INTERNAL $ $ K INT (CE = 0) or EXT (CE = 1) $ $ Figure 9 DSP56311 Memory Map MS = 0 and SC = 0 Memory Swich Mode Disabled, Sixeen-bi Compaibiliy Mode Disabled PROG X DATA Y DATA $FFFFFF INTERNAL $FFFFFF $FFFF80 (128 words) $FFFFFF $FFFFC0 $FFFF80 I/O $FF00C0 $FF0000 BOOTSTRAP ROM (192 words) $FFF000 $FF0000 INTERNAL $FFF000 $FF0000 INTERNAL $ $ $ K INTERNAL P 80K INTERNAL 80K INTERNAL $ $ K INT (CE = 0) or EXT (CE = 1) $ $ Figure 10 DSP56321 Memory Map MSW= 000 and SC = 0 Memory Swich Mode Disabled, Sixeen-bi Compaibiliy Mode Disabled Freescale Semiconducor 9

10 Memory Mapping PROG X DATA Y DATA $FFFF $FFFF $FF80 (128 words) $FFFF $FFC0 $FF80 I/O $C000 $C000 $ K INTERNAL P 48K INTERNAL 48K INTERNAL $0400 $0000 1K INT (CE = 0) or EXT (CE = 1) $0000 $0000 Figure 11 DSP56311 Memory Map MS = 0 and SC = 1 Memory Swich Mode Disabled, Sixeen-bi Compaibiliy Mode Enabled PROG X DATA Y DATA $FFFF $FFFF $FF80 (128 words) $FFFF $FFC0 $FF80 I/O $ K INTERNAL P 64K 128 INTERNAL 64K 128 INTERNAL $0400 $0000 1K INT (CE = 0) or EXT (CE = 1) $0000 $0000 Figure 12 DSP56321 Memory Map MSW = 000 and SC = 1 Memory Swich Mode Disabled, Sixeen-bi Compaibiliy Mode Enabled 10 Freescale Semiconducor

11 Memory Mapping PROG X DATA Y DATA $FFFFFF $FF00C0 $FF0000 INTERNAL BOOTSTRAP ROM (192 words) $FFFFFF $FFFF80 $FFF000 $FF0000 (128 words) INTERNAL $FFFFFF $FFFFC0 $FFFF80 $FFF000 $FF0000 I/O INTERNAL $ $00C000 $00C000 $ $ UP TO 95K INTERNAL P VIA MSW[1 0] 1K INT (CE = 0) or EXT (CE = 1) $00A000 $ UP TO 40K INTERNAL VIA MSW[1 0] $00A000 $ UP TO 40K INTERNAL VIA MSW[1 0] Figure 13 DSP56311 Memory Map MS = 1 and SC = 0 Memory Swich Mode Enabled, Sixeen-bi Compaibiliy Mode Disabled PROG X DATA Y DATA $FFFFFF $FF00C0 $FF0000 INTERNAL BOOTSTRAP ROM (192 words) $FFFFFF $FFFF80 $FFF000 $FF0000 (128 words) INTERNAL $FFFFFF $FFFFC0 $FFFF80 $FFF000 $FF0000 I/O INTERNAL $01C000 $ $ $ $ UP TO 111K INTERNAL P VIA MSW[2 0] 1K INT (CE = 0) or EXT (CE = 1) $ UP TO 80K INTERNAL VIA MSW[2 0] $ UP TO 80K INTERNAL VIA MSW[2 0] Figure 14 DSP56321 Memory Map MSW 000 and SC = 0 Memory Swich Mode Enabled, Sixeen-bi Compaibiliy Mode Disabled Freescale Semiconducor 11

12 EFCOP/Core Shared Memory PROG X DATA Y DATA $FFFF $FFFF $FF80 (128 words) $FFFF $FFC0 $FF80 I/O UP TO 63 K INTERNAL P VIA MSW[1 0] $C000 $C000 $A000 $A000 $0400 $0000 1K INT (CE = 0) or EXT (CE = 1) $0000 UP TO 40K INTERNAL VIA MSW[1 0] $0000 UP TO 40K INTERNAL VIA MSW[1 0] Figure 15 DSP56311 Memory Map MS = 1 and SC = 1 Memory Swich Enabled, Sixeen-bi Compaibiliy Mode Enabled PROG X DATA Y DATA $FFFF $FFFF $FF80 (128 words) $FFFF $FFC0 $FF80 I/O UP TO 63 K INTERNAL P VIA MSW[2 0] $0400 $0000 1K INT (CE = 0) or EXT (CE = 1) $0000 UP TO (64 K 128) INTERNAL VIA MSW[2 0] $0000 UP TO (64 K 128) INTERNAL VIA MSW[2 0] Figure 16 DSP56321 Memory Map MSW 000 and SC = 1 Memory Swich Enabled, Sixeen-bi Compaibiliy Mode Enabled 10 EFCOP/Core Shared Memory In he DSP56311, he EFCOP shares 20 K 24-bi words of memory wih he DSP core: 10 K words in he X-daa memory and 10 K words in he Y-daa memory In he DSP56321, he EFCOP shares 24 K words of memory wih he DSP core: 12 K words in he X-daa memory and 12 K words in he Y-daa memory 12 Freescale Semiconducor

13 S Access Wai Saes 11 S Access Wai Saes The DSP56311 requires wo wai saes for operaion a 150 MHz The daa shee for he DSP56321 S saes ha accesses require a minimum of hree wai saes for operaion a 275 MHz In addiion, if he Bus Conrol Regiser is configured for more han one wai sae, he DSP adds one or wo railing wai saes Table 6 shows he number of railing wai saes associaed wih he number of wai saes configured in he Bus Conrol Regiser for he DSP56311 or DSP56321 Table 6 Addiional Trailing Wai Saes for DSP56311 or DSP56321 Wai Saes in he Bus Conrol Regiser Addiional Trailing Wai Saes for DSP56311 or DSP (DSP56311) or 3 7 (DSP56321) D Suppor The DSP56311 suppors D access up o 100 MHz The DSP56321 does no suppor D access CLKOUT, BCLK, BCLK, CAS, and RAS[0 3] signals are no suppored 13 Operaing Mode Regiser In he DSP56311, bis 22, 21, and 7 in he OMR are MSW[1 0] and MS In he DSP56321, hese bis are MSW[2 0] This enables more swich modes in he DSP56321 The defaul mode represened by MS = 0 in he DSP56311 is represened by MSW[2 0] = 000 in he DSP56321 In addiion, because BCLK and BCLK suppor is removed, OMR bi 15 is undefined in he DSP56321, since Address Trace Mode is no suppored Figure 17 and Figure 18 show he OMR layous for he DSP56311 and DSP56321, respecively SCS EOM COM MSW[1 0] SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP1 0 MS SD EBD MD MC MB MA - Reserved bi; read zero; wrie zero for fuure compaibiliy Figure 17 DSP56311 Operaing Mode Regiser (OMR) Forma SCS EOM COM MSW[2 1] SEN WRP EOV EUN XYS APD ABE BRT TAS BE CDP1 0 MSW0 SD EBD MD MC MB MA - Reserved bi; read zero; wrie zero for fuure compaibiliy Figure 18 DSP56321 Operaing Mode Regiser (OMR) Forma Freescale Semiconducor 13

14 Clock/PLL 14 Clock/PLL The DSP56311 uses an inernal clock circuiry ha includes he sandard DSP56300 Phase Lock Loop (PLL) circui and clock generaor block The DSP56321 uses a new inernal clock circui design ha includes a DPLL and a new clock generaor circui Table 7 liss he differences beween he clock/pll and he clock/dpll circuis Table 7 DSP56311 Clock/PLL and DSP56321 Clock/DPLL Differences Characerisic DSP56311 Clock and PLL DSP56321 Clock and DPLL Inpu frequency (EXTAL) wih PLL disabled MHz MHz Inpu frequency (EXTAL) wih PLL enabled 7324 KHz o 150 MHz 16 MHz o 275 MHz Predivider Range (PDF) 1 o 16 1 o 16 1 Muliplier Range (MF) 1 o o 15 2 Core frequency maximum 150 MHz 275 MHz Core frequency in bypass mode EXTAL/2 EXTAL/2 Noes: 1 The oupu frequency from he predivider mus be beween MHz The minimum inpu frequency wih he PLL enabled mus be 16 MHz wih PDF = 1 The defaul PDF value a rese is 1 2 MF = MFI + MFN/MFD, where MFI = 5 o 15; MFN = 0 o 127; MFD = 1 o 128; and MFN < MFD Because he MF value is limied o a maximum of 15, if MFI = 15, MFN mus equal 0 See Secion 15for deailed informaion 15 PLL/DPLL Conrol Regisers The DSP56311 uses one PLL Conrol Regiser (see Figure 19 and Table 8) which is X-I/O-mapped a address $FFFFFD (24-bi mode) or $FFFD (16-bi mode) This read/wrie regiser direcs he operaion of he on-chip PLL PD3 PD2 PD1 PD0 COD PEN PSTP XTLD XTLR DF2 DF1 DF MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MF0 Figure 19 PLL Conrol Regiser (PCTL) Table 8 defines he DSP56311 PCTL bis Table 8 DSP56311 PLL Conrol Regiser (PCTL) Bi Definiions Bi Number Bi Name Rese Value Descripion PD[3 0] 0 Predivider Facor Bis Define he predivision facor (PDF) o be applied o he PLL inpu frequency The PD[3 0] bis are cleared during DSP56311 hardware rese, which corresponds o a PDF of one 19 COD 0 Clock Oupu Disable Conrols he oupu buffer of he clock a he CLKOUT pin When COD is se, he CLKOUT oupu is pulled high When COD is cleared, he CLKOUT pin provides a 50 percen duy cycle clock 18 PEN PINIT PLL Enable Enables PLL operaion The rese value is aken from he PINIT inpu 17 PSTP 0 PLL Sop Sae Conrols PLL and on-chip crysal oscillaor behavior during he sop processing sae 16 XTLD 0 XTAL Disable Conrols he on-chip crysal oscillaor XTAL oupu The XTLD bi is cleared during DSP56311 hardware rese, so he XTAL oupu signal is acive, permiing normal operaion of he crysal oscillaor 14 Freescale Semiconducor

15 Table 8 DSP56311 PLL Conrol Regiser (PCTL) Bi Definiions (Coninued) Bi Number Bi Name Rese Value Descripion PLL/DPLL Conrol Regisers 15 XTLR 0 Crysal Range Conrols he on-chip crysal oscillaor ransconducance The XTLR bi is se o a predeermined value during hardware rese In he DSP56311, his value is zero DF[2 0] 0 Division Facor Define he DF of he low-power divider These bis specify he DF as a power of wo in he range from 2 0 o MF[11 0] 0 PLL Muliplicaion Facor Define he muliplicaion facor ha is applied o he PLL inpu frequency The MF bis are cleared during DSP56311 hardware rese and hus correspond o an MF of one The DSP56321 uses wo conrol regisers: DPLL Saic Conrol Regiser (DSCR) a X:$FFFFD0 or X:FFD0 (16- bi mode) (see Figure 20 and Table 9) and he DPLL Clock Conrol Regiser (PCTL) a X:$FFFFD1 or X:FFD1 (16-bi mode) (see Figure 21 and Table 10) BRMO PLM PDF3 PDF2 PDF1 PDF0 MFD6 MFD5 MFD4 MFD3 MFD2 MFD MFD0 MFN6 MFN5 MFN4 MFN3 MFN2 MFN1 MFN0 MFI3 MFI2 MFI1 MFI0 Figure 20 DPLL Saic Conrol Regiser (DSCR) X:$FFFFD0 Bi Number Bi Name Table 9 DPLL Saic Conrol Regiser (DSCR) Bi Definiions Rese Value Descripion 23 BRMO 1 Binary Rae Modulaion Order The value of BRMO deermines he oupu order used by he Binary Rae Modulaor (BRM) If BRMO is cleared (0), he BRM uses a firs order oupu If BRMO is se (1), he BRM uses a second order oupu If he DPLL Muliplicaion Facor Denominaor (MFD) is < 8, hen use a firs order oupu (ha is, BRMO = 0) If MFD > 8, use a second order oupu (ha is, BRMO = 1) If he DPLL Muliplicaion Facor Numeraor (MFN) is 0, his bi is ignored Noes: The DPLL does no operae correcly if his bi is no configured appropriaely 22 PLM 1 Phase Lock Mode When his bi is cleared (0), he DPLL operaes in Frequency Only Lock (FOL) mode When his bi is se (1), he DPLL operaes in Frequency and Phase Lock (FPL) mode FPL mode can be used for boh an ineger and fracional muliplicaion facor, bu phase skew reducion is accomplished only for he ineger MF Freescale Semiconducor 15

16 PLL/DPLL Conrol Regisers Bi Number Bi Name Table 9 DPLL Saic Conrol Regiser (DSCR) Bi Definiions (Coninued) Rese Value PDF[3 0] 0 Predivision Facor (PDF) Defines he DPLL Predivision Facor value This value is in he range 1 16 Noes: The value of PDF bis wrien ino DSCR mus be he facor value minus 1 PDF[3 0] PDF Value MFD[6 0] 0 Muliplicaion Facor Denominaor (MFD) Defines he denominaor of he fracional par of he Muliplicaion Facor (MF) The MFD can be any ineger from 1 o 128 Noes: The value of MFD bis wrien ino DSCR mus be he denominaor value minus 1 The MFD value mus be higher han he MFN value MFD[6 0] Descripion MFD Value $00 1 $01 2 $02 3 $7E 127 $7F MFN[6 0] 0 Muliplicaion Facor Numeraor (MFN) Defines he numeraor of he fracional par of he MF The MFN can be any ineger from 0 o 127 Noes: The oal MF is limied o a maximum of 15 Therefore, if he MFI is programmed as 15 (ha is, MFI[3 0] = 1111), MFN mus equal 0 MFN[6 0] MFN Value $00 0 $01 1 $02 2 $7E 126 $7F Freescale Semiconducor

17 Bi Number Bi Name Table 9 DPLL Saic Conrol Regiser (DSCR) Bi Definiions (Coninued) Rese Value Descripion PLL/DPLL Conrol Regisers 3 0 MFI[3 0] 1000 Muliplicaion Facor Ineger (MFI) Defines he ineger par of he MF The MFI can be any ineger from 5 o 15 Noes: The oal MF is limied o a maximum of 15 Therefore, if he MFI is programmed as 15 (ha is, MFI[3 0] = 1111), MFN mus equal 0 MFI[3 0] MFI Value DF2 DF1 DF0 PEN XTLD PSTP Reserved, wrie as zeros o mainain fuure compaibiliy Figure 21 DPLL Clock Conrol Regiser (PCTL) Bi Number Bi Name Rese Value Table 10 DPLL Clock Conrol Regiser (PCTL) Descripion 23 7 reserved 0 These bis are reserved for fuure purposes Freescale Semiconducor 17

18 PLL/DPLL Conrol Regisers Table 10 DPLL Clock Conrol Regiser (PCTL) (Coninued) Bi Number Bi Name Rese Value Descripion 6 4 DF[2 0] 011 Division Facor (DF) Defines he low-power divider specified as a power of wo in he range from 2 0 o 2 7 Changing he value of he DF[2 0] bis does no cause a loss of lock condiion DF[2 0] DF value PEN PINIT DPLL Enable When PEN is se, he DPLL is enabled; when he DPLL locks, he inernal clocks are derived from he DPLL oupu When PEN is cleared, he inernal clocks are derived direcly from he EXTAL signal Disabling he DPLL minimizes power consumpion Sofware can se or clear he PEN bi a any ime during he device operaion During hardware rese, his bi is se or cleared based on he value of he DPLL PINIT inpu 2 XTLD 0 XTAL Disable Conrols he XTAL oupu from he crysal oscillaor on-chip driver When XTLD is cleared, he XTAL oupu pin is acive, permiing normal operaion of he crysal oscillaor When XTLD is se, he XTAL oupu pin is pulled high, disabling he on-chip oscillaor driver If he on-chip crysal oscillaor driver is no used (ha is, EXTAL is driven from an exernal clock source), se XTLD (disabling XTAL) o minimize RFI noise and power dissipaion 1 PSTP 0 DPLL Sop Sae Conrol Deermines DPLL and on-chip crysal oscillaor behavior during he Sop processing sae When PSTP is se, he DPLL and he onchip crysal oscillaor remain operaing when he chip is in he Sop sae When PSTP is cleared and he device eners he Sop sae, he DPLL and he on-chip crysal oscillaor are disabled o reduce power consumpion; however, his resuls in longer recovery ime upon exi from he Sop sae To enable rapid recovery when exiing he Sop sae (bu a he cos of higher power consumpion during he Sop sae), PSTP should be se Noes: PSTP and PEN are relaed When PSTP is se and PEN is cleared, he on-chip crysal oscillaor remains operaing in he Sop sae, bu he DPLL is disabled This power saving feaure enables rapid recovery from he Sop sae when you operae he device wih an on-chip oscillaor and wih he DPLL disabled PSTP PEN Operaion during Sop Sae DPLL Oscillaor (XTLD=0) Recovery Time from Sop Sae Power Consumpion during Sop Sae 0 X Disabled Disabled Long Minimal 1 0 Disabled Enabled Shor Low 1 1 Enabled Enabled Shor High 18 Freescale Semiconducor

19 Peripheral Timing Table 10 DPLL Clock Conrol Regiser (PCTL) (Coninued) Bi Number Bi Name Rese Value 0 reserved 0 This bi is reserved Descripion Noes: Alhough his bi is cleared afer rese, i enables he oupu of a reserved signal ha Freescale uses for developmen purposes To preven possible noise generaion, Freescale recommends wriing a 1 o his bi afer rese o disable he reserved signal oupu 16 Peripheral Timing The iming for he on-chip peripherals is based primarily on he operaing frequency used by he specified device (DSP56311 or DSP56321) An example of he effec due o he frequency difference is he raio of he peripheral clock frequency o he core clock frequency In addiion, inernal signal delay values are inherenly differen for he HiP4 process (DSP56311) versus he HiP7 process (DSP56321), resuling in differen consan values used in iming expressions Refer o Secion 2 in he DSP56311 Technical Daa shee or he DSP56321 Technical Daa shee for deailed iming informaion 17 Package The DSP56311 and DSP56321 are signal pin-compaible, bu he DSP56311 uses a 15 mm 15 mm 196-pin Molded Array Process-Ball Grid Array (MAP-BGA) package, whereas he DSP56321 uses Freescale s 15 mm 15 mm 196-pin Flip Chip-Ball Grid Array (FC-PBGA) package Table 11 summarizes he differences beween hese wo packages Table 11 Differences Beween he 196-Pin MAP-BGA and FC-PBGA Packages Characerisic MAP-BGA (DSP56311) FC-PBGA (DSP56321) X/Y Dimensions mm mm Ball Pich 10 mm 10 mm Pinou 196-pin 196-pin Inerconnecion Mehod Wirebond MAP-BGA is aached o he subsrae face-up, conneced using gold wires C4 Bump FC-PBGA uses an evaporaed 97% Lead/3% Tin (97Pb3Sn) bump joined o he subsrae face-down Package Heigh 160 mm maximum 243 mm maximum Θ JA ( C/W) 49 (no airflow) 50 (no airflow) simulaed Acual daa TBD Θ Jc ( C/W) simulaed Acual daa TBD Moisure Sensiiviy Moisure Sensiiviy Level 3 (MSL3) MSL5 capable Acual performance TBD capable Coplanariy Specificaion 010 mm 015 mm Package Sealing Agains Moisure Overmolded wih a dense silica epoxy Epoxy underfill seals he caviy beween die and subsrae and increases he reliabiliy of he bump inerconnecion Singulaion Saw cuing Flip chip subsraes are delivered singulaed from he subsrae supplier Package Idenifier VF FC Solder Balls 05 mm 62Sn36Pb2Ag 05 mm 62Sn36Pb2Ag Package Solder Pad Soldermask Defined (SMD) Soldermask Defined (SMD) Freescale Semiconducor 19

20 Package For dimensional reference, Figure 22 shows he MAP-BGA package drawing, and Figure 23 shows he FC-PBGA package drawing CASE 1128C-01 ISSUE O DATE: 07/28/98 Figure 22 Mechanical Informaion for 196-pin MAP-BGA Package 20 Freescale Semiconducor

21 Package NOTES: 1 DIMENSIONS IN MILLIMETERS 2 DIMENSIONS AND TOLERANCING PER ASME Y145, DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A 4 DATUM A THE SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS 5 D2 AND E2 DEFINE THE AREA OCCUPIED BY THE DIE Millimeers DIM MIN MAX 243 A A1 A2 A b D D1 15 BSC 13 REF D2 93 e E E1 1 BSC 15 BSC 13 REF E2 5 CASE 1128F-01 ISSUE A DATE: 06/08/01 Figure 23 Mechanical Informaion for 196-pin FC-PBGA Package Freescale Semiconducor 21

22 Package 22 Freescale Semiconducor

23 Package Freescale Semiconducor 23

24 How o Reach Us: Home Page: wwwfreescalecom suppor@freescalecom USA/Europe or Locaions no lised: Freescale Semiconducor Technical Informaion Cener, CH N Alma School Road Chandler, Arizona or suppor@freescalecom Europe, Middle Eas, and Africa: Freescale Halbleier Deuschland GMBH Technical Informaion Cener Schazbogen München, Germany (English) (English) (German) (French) suppor@freescalecom Japan: Freescale Semiconducor Japan Ld Headquarers ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo , Japan or supporjapan@freescalecom Asia/Pacific: Freescale Semiconducor Hong Kong Ld Technical Informaion Cener 2 Dai King Sree Tai Po Indusrial Esae Tai Po, NT Hong Kong Informaion in his documen is provided solely o enable sysem and sofware implemeners o use Freescale Semiconducor producs There are no express or implied copyrigh licenses graned hereunder o design or fabricae any inegraed circuis or inegraed circuis based on he informaion in his documen Freescale Semiconducor reserves he righ o make changes wihou furher noice o any producs herein Freescale Semiconducor makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does Freescale Semiconducor assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion consequenial or incidenal damages Typical parameers which may be provided in Freescale Semiconducor daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers Freescale Semiconducor does no convey any license under is paen righs nor he righs of ohers Freescale Semiconducor producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he Freescale Semiconducor produc could creae a siuaion where personal injury or deah may occur Should Buyer purchase or use Freescale Semiconducor producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold Freescale Semiconducor and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha Freescale Semiconducor was negligen regarding he design or manufacure of he par Freescale and he Freescale logo are rademarks of Freescale Semiconducor, Inc SarCore is a licensed rademark of SarCore LLC All oher produc or service names are he propery of heir respecive owners Freescale Semiconducor, Inc 2001, 2005 For Lieraure Requess Only: Freescale Semiconducor Lieraure Disribuion Cener PO Box 5405 Denver, Colorado or Fax: LDCForFreescaleSemiconducor@hibbergroupcom Documen Order No: EB365 Rev 5 10/2005