MUX 1. GENERAL DESCRIPTION

Transcription

1 256Mb Async./Burs/Sync./A/D MUX 1. GENERAL DESCRIPTION Winbond x16 ADMUX producs are high-speed, CMOS pseudo-saic random access memory developed for lowpower, porable applicaions. The device has a DRAM core organized. These devices are a variaion of he indusrysandard Flash conrol inerface, wih a muliplexed address/daa bus. The muliplexed address and daa funcionaliy dramaically reduce he required signal coun, and increase READ/WRITE bandwidh. For seamless operaion on a burs Flash bus, Winbond x16 ADMUX producs incorporae a ransparen self-refresh mechanism. The hidden refresh requires no addiional suppor from he sysem memory conroller and has no significan impac on device READ/WRITE performance. Two user-accessible conrol regisers define device operaion. The bus configuraion regiser (BCR) defines how he Winbond x16 ADMUX device ineracs wih he sysem memory bus and is nearly idenical o is counerpar on burs mode Flash devices. The refresh configuraion regiser (RCR) is used o conrol how refresh is performed on he DRAM array. These regisers are auomaically loaded wih defaul seings during power-up and can be updaed anyime during normal operaion. Special aenion has been focused on sandby curren consumpion during self refresh. Winbond x16 ADMUX producs include wo mechanisms o minimize sandby curren. Parial-array refresh (PAR) enables he sysem o limi refresh o only ha par of he DRAM array ha conains essenial daa. Temperaure-compensaed refresh (TCR) uses an on-chip sensor o adjus he refresh rae o mach he device emperaure he refresh rae decreases a lower emperaures o minimize curren consumpion during sandby. The sysem-configurable refresh mechanisms are accessed hrough he RCR. Winbond x16 ADMUX is complian wih he indusry-sandard CellularRAM 1.5 x16 A/D MUX. 2. FEATURES Suppors asynchronous and burs operaions VCC, VCCQ Volages: 1.7V 1.95V VCC 1.7V 1.95V VCCQ Random access ime: 70ns Burs mode READ and WRITE access: 4, 8, 16, or 32 words, or coninuous burs Burs wrap or sequenial Max clock rae: 133 MHz (CLK = 7.5ns) Low power consumpion: Asynchronous READ: <25 ma Coninuous burs READ: <35 ma Sandby curren: 400μA Low-power feaures On-chip emperaure compensaed refresh (TCR) Parial array refresh (PAR) Deep power-down (DPD) mode Package: 54 Ball VFBGA 16-bi muliplexed address/daa bus Operaing emperaure range : -40 C~85 C Publicaion Release Dae : June 27, Revision : A01-003

2 3. ORDERING INFORMATION 256Mb Async./Burs/Sync./A/D MUX Par Number VDD/VDDQ I/O Widh Type Ohers W958D6DBCX7I 1.8/1.8 x16 PKG CRAM A/D MUX,133MHz, -40 C~85 C Publicaion Release Dae : June 27, Revision : A01-003

3 256Mb Async./Burs/Sync./A/D MUX TABLE OF CONTENTS 1. GENERAL DESCRIPTION FEATURES ORDERING INFORMATION PIN CONFIGURATION Ball Assignmen PIN DESCRIPTION Signal Descripion BLOCK DIAGRAM INSTRUCTION SET Bus Operaion FUNCTIONAL DESCRIPTION Power Up Iniializaion Power-Up Iniializaion Timing Bus Operaing Modes Asynchronous Modes READ Operaion (ADV# LOW) WRITE Operaion (ADV# LOW) Burs Mode Operaion Burs Mode READ (4-word burs) Burs Mode WRITE (4-word burs) Refresh Collision During Variable-Laency READ Operaion Mixed-Mode Operaion WAIT Operaion Wired-OR WAIT Configuraion LB#/ UB# Operaion Low Power Operaion Sandby Mode Operaion Temperaure Compensaed Refresh Parial-Array Refresh Deep Power-Down Operaion Regisers Access Using CRE Configuraion Regiser WRITE Asynchronous Mode Followed by READ Operaion Configuraion Regiser WRITE Synchronous Mode Followed by READ Operaion Regiser READ Asynchronous Mode Followed by READ ARRAY Operaion Regiser READ Synchronous Mode Followed by READ ARRAY Operaion Sofware Access Load Configuraion Regiser Read Configuraion Regiser Bus Configuraion Regiser Bus Configuraion Regiser Definiion Burs Lengh (BCR[2:0]) Defaul = Coninuous Burs Burs Wrap (BCR[3]) Defaul = No Wrap Sequence and Burs Lengh Drive Srengh (BCR[5:4]) Defaul = Oupus Use Half-Drive Srengh Table of Drive Srengh WAIT Configuraion. (BCR[8]) WAIT Polariy (BCR[10]) WAIT Configuraion During Burs Operaion Laency Couner (BCR[13:11]) Defaul = Three Clock Laency Iniial Access Laency (BRC[14]) Defaul = Variable Allowed Laency Couner Seings in Variable Laency Mode Laency Couner (Variable Iniial Laency, No Refresh Collision) Allowed Laency Couner Seings in Fixed Laency Mode Laency Couner (Fixed Laency) Publicaion Release Dae : June 27, Revision : A01-003

4 256Mb Async./Burs/Sync./A/D MUX Operaing Mode (BCR[15]) Refresh Configuraion Regiser Refresh Configuraion Regiser Mapping Parial Array Refresh (RCR[2:0]) Defaul = Full Array Refresh Address Paerns for PAR (RCR [4] = 1) Deep Power-Down (RCR[4]) Defaul = DPD Disabled Device Idenificaion Regiser Device Idenificaion Regiser Mapping Virual Chip Enable Funcion: ELECTRICAL CHARACTERISTIC Absolue Maximum DC, AC Raings Elecrical Characerisics and Operaing Condiions Parial Array Self Refresh Sandby Curren Capaciance AC Inpu-Oupu Reference Wave form AC Oupu Load Circui TIMING REQUIRMENTS Read, Wrie Timing Requiremens Asynchronous READ Cycle Timing Requiremens Burs READ Cycle Timing Requiremens Asynchronous WRITE Cycle Timing Requiremens Burs WRITE Cycle Timing Requiremens TIMING DIAGRAMS Iniializaion Period DPD Enry and Exi Timing Parameers Iniializaion and DPD Timing Parameers Asynchronous READ Single Access Burs READ Operaion - Variable Laency Four Word Burs READ Operaion-Variable Laency Single-Access Burs READ Operaion-Fixed Laency Four Word Burs READ Operaion-Fixed Laency Burs READ Terminae a End-of-Row (Wrap Off) Burs READ Row Boundary Crossing Asynchronous WRITE Burs WRITE Operaion Variable Laency Mode Burs WRITE Operaion-Fixed Laency Mode Burs WRITE Terminae a End of Row (Wrap Off) Burs WRITE Row Boundary Crossing Burs WRITE Followed by Burs READ Asynchronous WRITE Followed by Burs READ Burs READ Followed by Asynchronous WRITE Asynchronous WRITE Followed by Asynchronous READ PACKAGE DESCRIPTION Package Dimension REVISION HISTORY Publicaion Release Dae : June 27, Revision : A01-003

5 256Mb Async./Burs/Sync./A/D MUX 4. PIN CONFIGURATION 4.1 Ball Assignmen A LB# OE# NC NC NC CRE B ADQ8 UB# NC NC CE# ADQ0 C ADQ9 ADQ10 NC NC ADQ1 ADQ2 D VSSQ ADQ11 A17 NC ADQ3 VCC E VCCQ ADQ12 A21 A16 ADQ4 VSS F ADQ14 ADQ13 NC NC ADQ5 ADQ6 G ADQ15 A19 NC NC WE# ADQ7 H A18 NC NC NC NC A20 J WAIT CLK ADV# A22 A23 NC (Top View) Pin Configuraion Publicaion Release Dae : June 27, Revision : A01-003

6 5. PIN DESCRIPTION 5.1 Signal Descripion Symbol Type Descripion A[max:16] CLK (Noe 1) ADV# (Noe 1) CRE CE# OE# WE# Inpu Inpu Inpu Inpu Inpu Inpu Inpu 256Mb Async./Burs/Sync./A/D MUX Address inpus: Inpus for addresses during READ and WRITE operaions. Addresses are inernally lached during READ and WRITE cycles. The address lines are also used o define he value o be loaded ino he BCR or he RCR. A[max:16]= A[23:16] (256Mb). Clock: Synchronizes he memory o he sysem operaing frequency during synchronous operaions. When configured for synchronous operaion, he address is lached on he firs rising CLK edge when ADV# is acive. CLK mus be saic (HIGH or LOW) during asynchronous access READ and WRITE operaions when burs mode is enabled. Address valid: Indicaes ha a valid address is presen on he address inpus. Addresses are lached on he rising edge of ADV# during asynchronous READ and WRITE operaions. Conrol regiser enable: When CRE is HIGH, WRITE operaions load he RCR or BCR, and READ operaions access he RCR, BCR, or DIDR. Chip enable: Acivaes he device when LOW. When CE# is HIGH, he device is disabled and goes ino sandby mode. Oupu enable: Enables he oupu buffers when LOW. When OE# is HIGH, he oupu buffers are disabled. LB# Inpu Lower bye enable. DQ[7:0]. Wrie enable: Deermines if a given cycle is a WRITE cycle. If WE# is LOW, he cycle is a WRITE o eiher a configuraion regiser or o he memory array. UB# Inpu Upper bye enable. DQ[15:8]. A/DQ[15:0] WAIT (Noe 1) Inpu/Oupu Oupu Address/daa I/Os: These pins are a muliplexed address/daa bus. As inpus for addresses, hese pins behave as A[15:0]. A[0] is he LSB of he 16-bi word address wihin he CellularRAM device. Address, RCR, and BCR values are loaded wih ADV# LOW. Daa is inpu or oupu when ADV# is HIGH. NC Reserved for fuure use. WAIT: Provides daa-valid feedback during burs READ and WRITE operaions. WAIT is used o arbirae collisions beween refresh and READ/WRITE operaions. WAIT is also assered a he end of a row unless wrapping wihin he burs lengh. WAIT should be ignored during asynchronous operaions. WAIT is High-Z when CE# is HIGH. VCC Supply Device power supply: Power supply for device core operaion. VCCQ Supply I/O power supply: Power supply for inpu/oupu buffers. VSS Supply VSS mus be conneced o ground. VSSQ Supply VSSQ mus be conneced o ground. Noes: 1. When using asynchronous mode exclusively, CLK can be ied o VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operaions. Publicaion Release Dae : June 27, Revision : A01-003

7 6. BLOCK DIAGRAM 256Mb Async./Burs/Sync./A/D MUX A[max:16] Address Decode Logic Refresh Configuraion Regiser (RCR) DRAM Memory Array Inpu / Oupu MUX and Buffers A/DQ [7:0] A/DQ [15:8] Device ID Regiser (DIDR) Bus Configuraion Regiser (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB# UB# Conrol Logic Inernal Exernal Publicaion Release Dae : June 27, Revision : A01-003

8 7. INSTRUCTION SET 7.1 Bus Operaion Asynchronous Mode BCR[15] = 1 (defaul) Power CLK ADV# CE# OE# WE# CRE 256Mb Async./Burs/Sync./A/D MUX LB#/ UB# WAIT*2 A/DQ[15:0]*3 Noes Read Acive X L L H L L Low-Z Daa ou 4 Wrie Acive X L X L L L High-Z Daa in 4 Sandby Sandby H or L X H X X L X High-Z High-Z 5, 6 No operaion Idle X X L X X L X Low-Z X 4, 6 Configuraion regiser WRITE Configuraion regiser READ DPD Burs Mode BCR[15] = 0 Acive X L H L H X Low-Z High-Z Acive X L L H H L Low-Z Config. reg. ou Deep powerdown X X H X X X X High-Z High-Z 10 Power CLK*1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT*2 A/DQ[15:0]*3 Noes Read Acive H or L L L H L L Low-Z Daa ou 4, 7 Wrie Acive H or L L X L L L High-Z Daa in 4 Sandby Sandby H or L X H X X L X High-Z High-Z 5, 6 No operaion Idle H or L X L X X L X Low-Z X 4, 6 Iniial burs READ Acive L L X H L L Low-Z Address 4, 8 Iniial burs WRITE Acive L L H L L X Low-Z Address 4, 8 Burs coninue Acive H L X X X L Low-Z Configuraion regiser WRITE Configuraion regiser READ DPD Daa in or Daa Acive L L H L H X Low-Z High-Z 8, 9 Acive L L L H H L Low-Z Config. reg. ou 8, 9 Deep powerdown L X H X X X X High-Z High-Z 10 Noes: 1. Wih burs mode enabled, CLK mus be saic (HIGH or LOW) during asynchronous READs and asynchronous WRITEs and o achieve sandby power during sandby mode. 2.The WAIT polariy is configured hrough he bus configuraion regiser (BCR[10]). 3.When LB# and UB# are in selec mode (LOW), DQ[15:0] are enabled. When only LB# is in selec mode, DQ[7:0] are enabled. When only UB# is in he selec mode, DQ[15:8] are enabled. 4.The device will consume acive power in his mode whenever addresses are changed. 5.When he device is in sandby mode, address inpus and daa inpus/oupus are inernally isolaed from any exernal influence. 6.VIN = VCCQ or 0V; all device balls mus be saic (unswiched) in order o achieve sandby curren. 7.When he BCR is configured for synchronous mode, synchronous READ and WRITE and asynchronous WRITE and READ are suppored. 8.Burs mode operaion is iniialized hrough he bus configuraion regiser (BCR[15]). 9.Iniial cycle. Following cycles are he same as BURST CONTINUE. CE# mus say LOW for he equivalen of a single-word burs (as indicaed by WAIT). 10. DPD is iniiaed when CE# ransiions from LOW o HIGH afer wriing RCR[4] o 0. DPD is mainained unil CE# ransiions from HIGH o LOW. ou 4, 8 Publicaion Release Dae : June 27, Revision : A01-003

9 256Mb Async./Burs/Sync./A/D MUX 8. FUNCTIONAL DESCRIPTION In general, ADMUX PSRAM devices are high-densiy alernaives o SRAM and Pseudo SRAM producs, popular in low-power, porable applicaions. Boh devices implemen a muliplexed address/daa bus. This muliplexed configuraion suppors greaer bandwidh hrough he x16 daa bus, ye sill reduces he required signal coun. The ADMUX PSRAM bus inerface suppors boh asynchronous and burs mode ransfers. 8.1 Power Up Iniializaion ADMUX PRAM producs include an on-chip volage sensor used o launch he power-up iniializaion process. Iniializaion will configure he BCR and he RCR wih heir defaul seings. VCC and VCCQ mus be applied simulaneously. When hey reach a sable level a or above 1.7V, he device will require 150μs o complee is selfiniializaion process. During he iniializaion period, CE# should remain HIGH. When iniializaion is complee, he device is ready for normal operaion Power-Up Iniializaion Timing Vcc VccQ Vcc=1.7v pu>=150us Device Iniializaion Device ready for normal operaion 8.2 Bus Operaing Modes This asynchronous/burs ADMUX PSRAM producs incorporae a burs mode inerface found on Flash producs argeing low-power, wireless applicaions. This bus inerface suppors asynchronous, and burs mode read and wrie ransfers. The specific inerface suppored is defined by he value loaded ino he BCR Asynchronous Modes Using indusry-sandard SRAM conrol signals (CE#, ADV#, OE#, WE#, and LB#/UB#). READ operaions are iniiaed by bringing CE#, ADV#, and LB#/UB# LOW while keeping OE# and WE# HIGH, and driving he address ono he A/DQ bus. ADV# is aken HIGH o capure he address, and OE# is aken LOW. daa will be driven ou of he I/Os afer he specified access ime has elapsed. WRITE operaions occur when CE#, ADV#, WE#, and LB#/UB# are driven LOW wih he address on he A/DQ bus. ADV# is aken HIGH o capure he address, hen he WRITE daa is driven ono he bus. During asynchronous WRITE operaions, he OE# level is a Don' Care, and WE# will override OE#; however, OE# mus be HIGH while he address is driven ono he A/DQ bus. The daa o be wrien is lached on he rising edge of CE#, WE#, UB#, or LB# (whichever occurs firs). During asynchronous operaion wih burs mode enabled, he CLK inpu mus be held saic (HIGH or LOW). WAIT will be driven during asynchronous READs, and is sae should be ignored. WE# LOW ime mus be limied o CEM. Publicaion Release Dae : June 27, Revision : A01-003

10 READ Operaion (ADV# LOW) 256Mb Async./Burs/Sync./A/D MUX A[max:16] Address CE# OE# WE# A/DQ[15:0] Address High- Z DATA ADV# LB#/UB# Don Care WRITE Operaion (ADV# LOW) A[max:16] Address CE# OE# WE# <CEM A/DQ[15:0] Address DATA ADV# LB#/UB# Don Care Undefined Publicaion Release Dae : June 27, Revision : A01-003

11 256Mb Async./Burs/Sync./A/D MUX Burs Mode Operaion Burs mode operaions enable high-speed synchronous READ and WRITE operaions. Burs operaions consis of a muli-clock sequence ha mus be performed in an ordered fashion. Afer CE# goes LOW, he address o access is lached on he firs CLK edge afer ADV# LOW. During his firs clock rising edge, WE# indicaes wheher he operaion is going o be a READ (WE# = HIGH) or WRITE (WE# =LOW) Burs Mode READ (4-word burs) CLK A[max:16] address ADV# CE# Laency Code 2(3 clocks) OE# WE# LB#/UB# A/DQ[15:0] address D0 D1 D2 D3 WAIT READ burs idenified (WE#=HIGH) Invalid Don Care Undefined Noe : Non-defaul BCR seings for burs mode READ (4-word burs): fixed or variable laency, Laency code 2 (3 clocks), WAIT acive Low, WAIT assered during delay. Diagram is represenaive of variable laency wih no refresh collision or fixedlaency access. Publicaion Release Dae : June 27, Revision : A01-003

12 Burs Mode WRITE (4-word burs) 256Mb Async./Burs/Sync./A/D MUX CLK A[max:16] address ADV# CE# Laency Code 2(3 clocks) OE# WE# LB#/UB# A/DQ[15:0] address D0 D1 D2 D3 WAIT WRITE burs idenified (WE#=LOW) Don Care Noe : Non-defaul BCR seings for burs mode WRITE (4-word burs) : fixed or variable laency, laency code 2(3 clocks), WAIT acive LOW, WAIT assered during delay. Publicaion Release Dae : June 27, Revision : A01-003

13 256Mb Async./Burs/Sync./A/D MUX The size of a burs can be specified in he BCR eiher as a fixed lengh or coninuous. Fixed-lengh burss consis of 4, 8, 16, or 32 words. Coninuous burss have he abiliy o sar a a specified address and burs o he end of he address. I goes back o he firs address and coninues o burs when coninuous burss mee he end of address. The laency coun sored in he BCR defines he number of clock cycles ha elapse before he iniial daa value is ransferred beween he processor and ADMUX PSRAM device. The iniial laency for READ operaions can be configured as fixed or variable (WRITE operaions always use fixed laency). Variable laency allows he ADMUX PSRAM o be configured for minimum laency a high clock frequencies, bu he conroller mus monior WAIT o deec any conflic wih refresh cycles. Fixed laency oupus he firs daa word afer he wors-case access delay, including allowance for refresh collisions. The iniial laency ime and clock speed deermine he laency coun seing. Fixed laency is used when he conroller canno monior WAIT. Fixed laency also provides improved performance a lower clock frequencies. The WAIT oupu assers when a burs is iniiaed, and de-assers o indicae when daa is o be ransferred ino (or ou of) he memory. WAIT will again be assered a he boundary of he row, unless wrapping wihin he burs lengh. Wih wrap off, he ADMUX PSRAM device will resore he previous row s daa and access he nex row, WAIT will be deassered, and he burs can coninue across he row boundary. If he burs is o erminae a he row boundary, CE# mus go HIGH wihin 2 clocks of he las daa. CE# mus go HIGH before any clock edge following he las word of a defined-lengh burs WRITE. The CE# LOW ime is limied by refresh consideraions. CE# mus no say LOW longer han CEM. If a burs suspension will cause CE# o remain LOW for longer han CEM, CE# should be aken HIGH and he burs resared wih a new CE# LOW/ADV# LOW cycle Refresh Collision During Variable-Laency READ Operaion CLK A[max:16] Address ADV# CE# OE# WE# LB#/UB# A/DQ[15:0] WAIT VOH VOL High-z Address VOH VOL D0 D1 D2 D3 Addiional WAIT saaes insered o allow refresh compleion Undefined Don Care Noe : Non-defaul BCR seings for refresh collision during variable-laency READ operaion : laency code 2(3 clocks), WAIT acive LOW, WAIT assered during delay. Publicaion Release Dae : June 27, Revision : A01-003

14 256Mb Async./Burs/Sync./A/D MUX Mixed-Mode Operaion The device suppors a combinaion of synchronous WRITE / READ and asynchronous WRITE / READ operaions when he BCR is configured for synchronous operaion. The asynchronous WRITE operaions require ha he clock (CLK) remain saic (HIGH or LOW) during he enire sequence. The ADV# signal can be used o lach he arge address, or i can remain LOW during he enire WRITE operaion. CE# can remain LOW when ransiioning beween mixed-mode operaions wih fixed laency enabled; however, he CE# LOW ime mus no exceed CEM. Mixed-mode operaion faciliaes a seamless inerface o legacy burs mode Flash memory conrollers WAIT Operaion The WAIT oupu on a ADMUX PSRAM device is ypically conneced o a shared, sysem level WAIT signal. The shared WAIT signal is used by he processor o coordinae ransacions wih muliple memories on he synchronous bus Wired-OR WAIT Configuraion CellularRAM WAIT Exernal Pull-Up/Pull-Down Resisor READY Processor WAIT Oher Device WAIT Oher Device When a burs READ or WRITE operaion has been iniiaed, WAIT goes acive o indicae ha he ADMUX PSRAM device requires addiional ime before daa can be ransferred. For READ operaions, WAIT will remain acive unil valid daa is oupu from he device. For WRITE operaions, WAIT will indicae o he memory conroller when daa will be acceped ino he ADMUX PSRAM device. When WAIT ransiions o an inacive sae, he daa burs will progress on successive clock edges. During a burs cycle, CE# mus remain assered unil he firs daa is valid. Bringing CE# HIGH during his iniial laency may cause daa corrupion. When using variable iniial access laency (BCR[14] = 0), he WAIT oupu performs an arbiraion role for burs READ operaions launched while an on-chip refresh is in progress. If a collision occurs, WAIT is assered for addiional clock cycles unil he refresh has compleed. When he refresh operaion has compleed, he burs READ operaion will coninue normally. WAIT is also assered when a coninuous READ or WRITE burs crosses a row boundary. The WAIT asserion allows ime for he new row o be accessed. WAIT will be assered afer OE# goes LOW during asynchronous READ operaions. WAIT will be High-Z during asynchronous WRITE operaions. WAIT should be ignored during all asynchronous operaions. By using fixed iniial laency (BCR[14] = 1), his ADMUX PSRAM device can be used in burs mode wihou monioring he WAIT signal. However, WAIT can sill be used o deermine when valid daa is available a he sar of he burs and a he end of he row. If WAIT is no moniored, he conroller mus sop burs accesses a row boundaries on is own. Publicaion Release Dae : June 27, Revision : A01-003

15 256Mb Async./Burs/Sync./A/D MUX LB#/ UB# Operaion The LB# enable and UB# enable signals suppor bye-wide daa WRITEs. During WRITE operaions, any disabled byes will no be ransferred o he RAM array and he inernal value will remain unchanged. During an asynchronous WRITE cycle, he daa o be wrien is lached on he rising edge of CE#, WE#, LB#, or UB#, whichever occurs firs. LB# and UB# mus be LOW during READ cycles. When boh he LB# and UB# are disabled (HIGH) during an operaion, he device will disable he daa bus from receiving or ransmiing daa. Alhough he device will seem o be deseleced, i remains in an acive mode as long as CE# remains LOW. 8.3 Low Power Operaion Sandby Mode Operaion During sandby, he device curren consumpion is reduced o he level necessary o perform he DRAM refresh operaion. Sandby operaion occurs when CE# is HIGH. The device will ener a reduced power sae upon compleion of a READ or WRITE operaion, or when he address and conrol inpus remain saic for an exended period of ime. This mode will coninue unil a change occurs o he address or conrol inpus Temperaure Compensaed Refresh Temperaure-compensaed refresh (TCR) allows for adequae refresh a differen emperaures. This ADMUX PSRAM device includes an on-chip emperaure sensor ha auomaically adjuss he refresh rae according o he operaing emperaure. The device coninually moniors he emperaure o selec an appropriae self-refresh rae Parial-Array Refresh Parial-array refresh (PAR) resrics refresh operaion o a porion of he oal memory array. This feaure enables he device o reduce sandby curren by refreshing only ha par of he memory array required by he hos sysem. The refresh opions are full array, one-half array, one-quarer array, one-eighh array, or none of he array. The mapping of hese pariions can sar a eiher he beginning or he end of he address map. READ and WRITE operaions o address ranges receiving refresh will no be affeced. Daa sored in addresses no receiving refresh will become corruped. When addiional porions of he array need o be re-enabled, he new porions are available immediaely afer he compleion of he WRITE cycle ha updaes he RCR wih he new configuraion Deep Power-Down Operaion Deep power-down (DPD) operaion disables all refresh-relaed aciviy. This mode is used if he sysem does no require he sorage provided by he ADMUX PSRAM device. Any sored daa will become corruped when DPD is enabled. When refresh aciviy has been re-enabled, he ADMUX PSRAM device will require 150μs o perform an iniializaion procedure before normal operaions can resume. During his 150μs period, he curren consumpion will be higher han he specified sandby levels, bu considerably lower han he acive curren specificaion. DPD can be enabled by wriing o he RCR using CRE or he sofware access sequence; DPD sars when CE# goes HIGH. DPD is disabled he nex ime CE# goes LOW and says LOW for a leas 10μs. Publicaion Release Dae : June 27, Revision : A01-003

16 256Mb Async./Burs/Sync./A/D MUX 8.4 Regisers Two user-accessible configuraion regisers define he device operaion. The bus configuraion regiser (BCR) defines how he ADMUX PSRAM ineracs wih he sysem memory bus and is nearly idenical o is counerpar on burs mode Flash devices. The refresh configuraion regiser (RCR) is used o conrol how refresh is performed on he DRAM array. These regisers are auomaically loaded wih defaul seings during power-up, and can be updaed any ime he devices are operaing in a sandby sae. A DIDR provides informaion on he device manufacurer, CellularRAM generaion, and he specific device configuraion. The DIDR is read-only Access Using CRE The regisers can be accessed using eiher a synchronous or an asynchronous operaion when he conrol regiser enable (CRE) inpu is HIGH. When CRE is LOW, a READ or WRITE operaion will access he memory array. The configuraion regiser values are wrien via addresses A[max:16] and ADQ[15:0]. In an asynchronous WRITE, he values are lached ino he configuraion regiser on he rising edge of ADV#, CE#, or WE#, whichever occurs firs; LB# and UB# are Don Care. The BCR is accessed when A[19:18] are 10b; he RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For reads, address inpus oher han A[19:18] are Don Care, and regiser bis 15:0 are oupu on DQ[15:0]. Immediaely afer performing a configuraion regiser READ or WRITE operaion, reading he memory array is highly recommended. Publicaion Release Dae : June 27, Revision : A01-003

17 Configuraion Regiser WRITE Asynchronous Mode Followed by READ Operaion 256Mb Async./Burs/Sync./A/D MUX A[max:16] (excep A[19:18]) A[19:18] 1 OPCODE AVS Selec conrol r regiser AVH Address Address CRE ADV# CE# OE# WE# AVS VP AVH Iniiae conrol regiser access CW WP Wrie address bus value o conrol regiser CPH LB#/UB# A/DQ[15:0] OPCODE Address daa Don Care Noes: 1. A[19:18] = 00b o load RCR, and 10b o load BCR. Publicaion Release Dae : June 27, Revision : A01-003

18 Configuraion Regiser WRITE Synchronous Mode Followed by READ Operaion 256Mb Async./Burs/Sync./A/D MUX CLK A [max :16] (excep A[19:18]) A[19:18] 2 Lach conrol regiser value OPCODE HD SP Lach conrol regiser address Address Address SP CRE HD ADV# SP HD CE # CSP Noes 3 CBPH OE# WE# SP HD LB#/UB# A/DQ [15:0] OPCODE KHTL Address Daa WAIT High-z High Z Don Care Noes: 1.Non-defaul BCR seings for synchronous mode configuraion regiser WRITE followed by READ ARRAY operaion: laency code 2 (3 clocks), WAIT acive LOW, WAIT assered during delay. 2. A/DQ[19:18] = 00b o load RCR, and 10b o load BCR. 3. CE# mus remain LOW o complee a burs-of-one WRITE. WAIT mus be moniored addiional WAIT cycles caused by refresh collisions require a corresponding number of addiional CE# LOW cycles. Publicaion Release Dae : June 27, Revision : A01-003

19 Regiser READ Asynchronous Mode Followed by READ ARRAY Operaion 256Mb Async./Burs/Sync./A/D MUX A [max:16] (excep A [ 19 :18]) A[19:18] 1 AVS Selec regiser AVH Address Address AA AVH CRE AVS AA ADV# VP AADV CPH CE# OE# CPH Iniiae regiser access CO HZ OE OHZ WE# LB#/UB# BA OLZ BHZ A/DQ [ 15 : 0 ] CR Address daa Don Care Undefined Noe : A / DQ [19:18] = 00b o read RCR, 10b o read BCR, and 01b o read DIDR. Publicaion Release Dae : June 27, Revision : A01-003

20 Regiser READ Synchronous Mode Followed by READ ARRAY Operaion CLK 256Mb Async./Burs/Sync./A/D MUX A[max:16 ] (excep A) [19 :18 ] Lach conrol regiser value Address A[19 :18 ] 2 SP Lach conrol regiser address Address HD SP CRE HD ADV# SP CE# CSP HD ABA Noe 3 CBPH OE # HZ WE # SP BOE HD OHZ LB #/UB # OLZ ACLK KOH A/DQ[15:0] CR Address daa WAIT High-Z KHTL High-Z Don Care Undefined Noes :1.Non-defaul BCR seings for synchronous mode regiser READ followed by READ ARRAY operaion : Laency code2(3 clocks) : WAIT acive LOW;WAIT assered during delay. 2.A[19:18]=00b o read RCR,10b o read BCR, and 01b o read DIDR. 3.CE# mus remain LOW o complee a burs-of-one READ. WAIT mus be moniored addiional WAIT cycles caused by refresh collisions require a corresponding number of addiional CE# LOW cycles. Publicaion Release Dae : June 27, Revision : A01-003

21 256Mb Async./Burs/Sync./A/D MUX Sofware Access Sofware access of he regisers uses a sequence of asynchronous READ and asynchronous WRITE operaions. The conens of he configuraion regisers can be modified and all regisers can be read using he sofware sequence. The configuraion regisers are loaded using a four-sep sequence consising of wo asynchronous READ operaions followed by wo asynchronous WRITE operaions. The read sequence is virually idenical excep ha an asynchronous READ is performed during he fourh operaion. The address used during all READ and WRITE operaions is he highes address of he ADMUX PSRAM device being accessed; he conens of his address are no changed by using his sequence. The daa value presened during he hird operaion (WRITE) in he sequence defines wheher he BCR, RCR, is o be accessed. If he daa is 0000h, he sequence will access he RCR; if he daa is 0001h, he sequence will access he BCR. During he fourh operaion, ADQ[15:0] ransfer daa in o or ou of bis 15:0 of he regisers. The use of he sofware sequence does no affec he abiliy o perform he sandard (CRE-conrolled) mehod of loading he configuraion regisers. However, he sofware naure of his access mechanism eliminaes he need for CRE. If he sofware mechanism is used, CRE can simply be ied o VSS. The por line ofen used for CRE conrol purposes is no longer required Load Configuraion Regiser CE# READ READ WRITE WRITE OE # WE # LB #/UB # ADV# A[max:16 ] Address (MAX) Address Address Address (MAX) (MAX) (MAX) A/DQ[15:0] Address (MAX) XXXX Address (MAX) 0ns (min) XXXX Address (MAX) Address (MAX) CR value in RCR:0000h BCR:0001h Don Care Publicaion Release Dae : June 27, Revision : A01-003

22 Read Configuraion Regiser CE# READ READ 256Mb Async./Burs/Sync./A/D MUX WRITE READ OE # WE # LB #/UB # ADV# A[max:16 ] Address (MAX) Address Address Address (MAX) (MAX) (MAX) A/DQ[15:0] Address (MAX) XXXX Address (MAX) 0ns (min) XXXX Address (MAX) Address (MAX) CR value ou RCR:0000h BCR:0001h DIDR:0002h Don Care Bus Configuraion Regiser The BCR defines how he ADMUX PSRAM device ineracs wih he sysem memory bus. A power-up, he BCR is se o 9D1Fh. The BCR is accessed wih CRE HIGH and A[19:18] = 10b, or hrough he regiser access sofware sequence wih A/DQ = 0001h on he hird cycle. Publicaion Release Dae : June 27, Revision : A01-003

23 Bus Configuraion Regiser Definiion 256Mb Async./Burs/Sync./A/D MUX A[max:20] A[19:18] A[17:16] A/DQ15 A/DQ14 A/DQ[13:11] A/DQ10 A/DQ9 A/DQ8 A/DQ7 A/DQ6 A/DQ5 A/DQ4 A/DQ3 A/DQ[2:0] max Regiser Reserved Reserved Operaing Iniial Laency WAIT Reserved WAIT Burs Burs Reserved Reserved Drive Srengh Selec Mode Laency Couner Polariy Configuraion ( WC ) Wrap(BW)* Lengh( BL)* All mus be se o " 0" Mus be se o "0" Mus be se o "0" Mus be se o "0" Mus be se o "0" Variable Fixed BCR[14] BCR[13] BCR[12] BCR[11] All ohers All ohers Laency code 2 code 3 ( defaul) code 4 Reserved code 2 code 3 code 4 code 5 code code 8 Reserved BCR[3] Burs Wrap ( Noe 1) 0 1 Burs wraps wihin he burs lengh Burs no wraps ( defaul) BCR[5] BCR[4] Drive Srengh Full 1/ 2 (defaul ) 1/ 4 reserved BCR[10] WAIT Polariy BCR[8] WAIT Configuraion 0 Acive Low 0 Assered during delay 1 Acive HIGH ( Defaul) 1 Assered one daa cycle before delay ( defaul) BCR[15] Operaing Mode 0 1 Synchronous burs access mode Asynchronous access mode ( Defaul) BCR[2] BCR[1] BCR[0] Burs Lengh ( Noe 1) 4 words BCR[19] BCR[18] Regiser Selec Selec RCR Selec BCR Selec DIDR Ohers 8 words 16 words 32 words Coninuous burs ( defaul) Reserved Noes: 1. Burs wrap and lengh apply o boh READ and WRITE operaions. 2.Reserved bis mus be se o zero. Reserved bis no se o zero will affec device funcionaliy. BCR[15:0] will be read back as wrien. Publicaion Release Dae : June 27, Revision : A01-003

24 256Mb Async./Burs/Sync./A/D MUX Burs Lengh (BCR[2:0]) Defaul = Coninuous Burs Burs lenghs define he number of words he device oupus during burs READ and WRITE operaions. The device suppors a burs lengh of 4, 8, 16, or 32 words. The device can also be se in coninuous burs mode where daa is oupu sequenially wihou regard o address boundaries; he inernal address wraps o h if he device is read pas he las address Burs Wrap (BCR[3]) Defaul = No Wrap The burs-wrap opion deermines if a 4-, 8-, 16-, or 32-word READ or WRITE burs wraps wihin he burs lengh, or seps hrough sequenial addresses. If he wrap opion is no enabled, he device accesses daa from sequenial addresses wihou regard o address boundaries; he inernal address wraps o h if he device is read pas he las address. Publicaion Release Dae : June 27, Revision : A01-003

25 Sequence and Burs Lengh Burs Wrap Sar Addr BCR[3] Wrap Decimal 4-Word 8-Word 16-Word Burs Burs Lengh Burs Lengh Lengh 256Mb Async./Burs/Sync./A/D MUX 32-Word Coninuous Burs Burs Lengh Linear Linear Linear Linear Linear Yes No Publicaion Release Dae : June 27, Revision : A01-003

26 256Mb Async./Burs/Sync./A/D MUX Drive Srengh (BCR[5:4]) Defaul = Oupus Use Half-Drive Srengh The oupu driver srengh can be alered o full, one-half, or one-quarer srengh o adjus for differen daa bus loading scenarios. The reduced-srengh opions are inended for sacked chip (Flash + ADMUX PSRAM ) environmens when here is a dedicaed memory bus. The reduced-drive-srengh opion minimizes he noise generaed on he daa bus during READ operaions. Full oupu drive srengh should be seleced when using a discree ADMUX PSRAM device in a more heavily loaded daa bus environmen. Oupus are configured a half-drive srengh during esing Table of Drive Srengh BCR[5] BCR[4] Drive Srengh Impedance Typ (Ω) Use Recommendaion 0 0 Full CL = 30pF o 50pF 0 1 1/2 (defaul) 50 CL = 15pF o 30pF 1 0 1/4 100 CL = 15pF or lower 1 1 Reserved WAIT Configuraion. (BCR[8]) Defaul =WAIT Transiions 1 Clock Before Daa / Invalid The WAIT configuraion bi is used o deermine when WAIT ransiions beween he assered and he de-assered sae wih respec o valid daa presened on he daa bus. The memory conroller will use he WAIT signal o coordinae daa ransfer during synchronous READ and WRITE operaions. When BCR[8] = 0, daa will be valid or invalid on he clock edge immediaely afer WAIT ransiions o he de-assered or assered sae, respecively. When BCR[8] = 1, he WAIT signal ransiions one clock period prior o he daa bus going valid or invalid WAIT Polariy (BCR[10]) Defaul = WAIT Acive HIGH The WAIT polariy bi indicaes wheher an assered WAIT oupu should be HIGH or LOW. This bi will deermine wheher he WAIT signal requires a pull-up or pull-down resisor o mainain he de-assered sae. The defaul value is BCR[10]=1, indicaing WAIT acive HIGH. Publicaion Release Dae : June 27, Revision : A01-003

27 WAIT Configuraion During Burs Operaion CLK WAIT WAIT 256Mb Async./Burs/Sync./A/D MUX BCR[8]=0 Daa vaild in curren cycle BCR[8]=1 Daa vaild in nex cycle A/DQ[15:0] Iniial laency D0 D1 D2 D3 Noe : Signals shown are for WAIT acive LOW, no wrap. End of row Don care Laency Couner (BCR[13:11]) Defaul = Three Clock Laency The laency couner bis deermine how many clocks occur beween he beginning of a READ or WRITE operaion and he firs daa value ransferred. For allowable laency codes, see he following ables and figures Iniial Access Laency (BRC[14]) Defaul = Variable Variable iniial access laency oupus daa afer he number of clocks se by he laency couner. However, WAIT mus be moniored o deec delays caused by collisions wih refresh operaions. Fixed iniial access laency oupus he firs daa a a consisen ime ha allows for wors-case refresh collisions. The laency couner mus be configured o mach he iniial laency and he clock frequency. I is no necessary o monior WAIT wih fixed iniial laency. The burs begins afer he number of clock cycles configured by he laency couner Allowed Laency Couner Seings in Variable Laency Mode BCR[13:11] Laency Configuraion Code Normal Laency *1 Maximum wih Refresh Collision Max Inpu CLK Frequency (MHz) (3 clocks) (15ns) 66 (15ns) 011 3(4clocks) defaul (9.62ns) 104 (9.62ns) (5 clocks) (7.5ns) Ohers Reserved Noes: 1.Laency is he number of clock cycles from he iniiaion of a burs operaion unil daa appears. Daa is ransferred on he nex clock cycle. Publicaion Release Dae : June 27, Revision : A01-003

28 Laency Couner (Variable Iniial Laency, No Refresh Collision) CLK 256Mb Async./Burs/Sync./A/D MUX A[max:16] address ADV# Code 2 A/DQ [15 :0] address oupu oupu oupu oupu oupu Code 3 (Defaul) A/DQ [15 :0] address Code 4 oupu oupu oupu oupu A/DQ [15 :0] address oupu oupu oupu Don Care Undefined Allowed Laency Couner Seings in Fixed Laency Mode BCR[13:11] Laency Configuraion Code Laency Coun (N) Max Inpu CLK Frequency (MHz) (3 clocks) 2 33 (30ns) 33 (30ns) (4 clocks) defaul 3 52 (19.2ns) 52 (19.2ns) (5 clocks) 4 66 (15ns) 66 (15ns) (6 clocks) 5 75 (13.3ns) 75 (13.3ns) (7 clocks) (9.62ns) 104 (9.62ns) (9 clocks) (7.5ns) Ohers Reserved Publicaion Release Dae : June 27, Revision : A01-003

29 Laency Couner (Fixed Laency) 256Mb Async./Burs/Sync./A/D MUX N-1 Cycles Cycle N CLK AA A [max :16] ADV # CE # address AADV CO A/DQ[15:0 ] ( READ ) ACLK oupu oupu oupu oupu oupu SP HD A/DQ[15:0 ] ( WRITE ) address inpu inpu inpu inpu inpu Burs Idenified (ADV # = LOW) Don Care Undefined Operaing Mode (BCR[15]) Defaul = Asynchronous Operaion The operaing mode bi selecs eiher synchronous burs operaion or he defaul asynchronous mode of operaion Refresh Configuraion Regiser The refresh configuraion regiser (RCR) defines how he ADMUX PSRAM device performs is ransparen self refresh. Alering he refresh parameers can dramaically reduce curren consumpion during sandby mode. A power-up, he RCR is se o 0010h. The RCR is accessed wih CRE HIGH and A[19:18] = 00b; or hrough he regiser access sofware sequence wih A/DQ = 0000h on he hird cycle. Publicaion Release Dae : June 27, Revision : A01-003

30 Refresh Configuraion Regiser Mapping A [max :20] A[19:18] A [17:16], ADQ [15: 7] ADQ6 256Mb Async./Burs/Sync./A/D MUX ADQ5 ADQ 4 ADQ3 ADQ2 ADQ1 ADQ0 max Reserved Regiser Selec Reserved Ignored DPD Reserved PAR All mus be se o 0 All mus be se o 0 Seing is ignored Mus be se o 0 RCR[19] RCR[18] Regiser Selec RCR[2] RCR[1] RCR[0] Refersh Coverage 0 0 Selsec RCR Full array(defaul) 1 0 Selsec BCR Boom 1/2 array 0 1 Selsec DIDR Boom 1/4 array Boom 1/ 8 array RCR [4] Deep Power - Down None of array 0 DPD Enable Top 1/2 array 1 DPD Disable (defaul) Top 1/4 array Top 1/8 array Noes : Reserved bis mus be se o zero. Reserved bis no se o zero will affec device funcionaliy. RCR[15:0] will be read back as wrien Parial Array Refresh (RCR[2:0]) Defaul = Full Array Refresh The PAR bis resric refresh operaion o a porion of he oal memory array. This feaure allows he device o reduce sandby curren by refreshing only ha par of he memory array required by he hos sysem. The refresh opions are full array, one-half array, one-quarer array, one-eighh array, or none of he array. The mapping of hese pariions can sar a eiher he beginning or he end of he address map. Publicaion Release Dae : June 27, Revision : A01-003

31 256Mb Async./Burs/Sync./A/D MUX Address Paerns for PAR (RCR [4] = 1) RCR[2] RCR[1] RCR[0] Acive Secion Address Space Size Densiy Full die h FFFFFFh 16 Meg x Mb One-half of die h 7FFFFFh 8 Meg x Mb One-quarer of die h 3FFFFFh 4 Meg x 16 64Mb One-eighh of die h 1FFFFFh 2 Meg x 16 32Mb None of die 0 0 Meg x 16 0Mb One-half of die h FFFFFFh 8 Meg x Mb One-quarer of die C00000h FFFFFFh 4 Meg x 16 64Mb One-eighh of die E00000h FFFFFFh 2 Meg x 16 32Mb Deep Power-Down (RCR[4]) Defaul = DPD Disabled The deep power-down bi enables and disables all refresh-relaed aciviy. This mode is used if he sysem does no require he sorage provided by he ADMUX PSRAM device. Any sored daa will become corruped when DPD is enabled. When refresh aciviy has been re-enabled, he CellularRAM device will require 150μs o perform an iniializaion procedure before normal operaions can resume. Deep power-down is enabled by seing RCR[4] = 0 and aking CE# HIGH. DPD can be enabled using CRE or he sofware sequence o access he RCR. Taking CE# LOW for a leas 10μs disables DPD and ses RCR[4] = 1; i is no necessary o wrie o he RCR o disable DPD. BCR and RCR values (oher han BCR[4]) are preserved during DPD Device Idenificaion Regiser The DIDR provides informaion on he device manufacurer, CellularRAM generaion, and he specific device configuraion. This regiser is read-only. The DIDR is accessed wih CRE HIGH and A[19:18] = 01b, or hrough he regiser access sofware sequence wih ADQ = 0002h on he hird cycle Device Idenificaion Regiser Mapping Bi Field DIDR[15] DIDR[14:11] DIDR[10:8] DIDR[7:5] DIDR[4:0] Field name Row lengh Device version Device densiy CellularRAM generaion Vendor ID Lengh Bi Seing Version Bi Seing Densiy Bi Seing Generaion Bi Seing Vendor Bi Seing Opions 256 words 1b 1s 0000b 256Mb 100b CR b Winbond 00110b 2nd 0001b Virual Chip Enable Funcion: A 512Mb device can be implemened by a MCP consising of wo sacked 256Mb devices wih Virual Chip Enable funcion. By proper configuraion, one 2568Mb device of he MCP is mapped o he lower 256Mb memory space of he 512Mb device and he anoher one 256Mb device is mapped o he upper 256Mb memory space of he 512Mb device. The 256Mb device wih Virual Chip Enable funcion provides a VCE inpu pin which is conrolled by he A24 (he MSB of address bus of 512Mb memory space). When he 256Mb device is mapped o he lower 256Mb memory space, he device will be acive if A24 is low. When he 256Mb device is mapped o he upper 256Mb memory space, he device will be acive if A24 is high. Publicaion Release Dae : June 27, Revision : A01-003

32 256Mb Async./Burs/Sync./A/D MUX 9. ELECTRICAL CHARACTERISTIC 9.1 Absolue Maximum DC, AC Raings Parameer Min Max Uni Operaing emperaure (case) Wireless ºC Sorage emperaure (plasic) ºC Soldering emperaure and ime 10s (solder ball only) +260 ºC Volage o any ball excep VCC, VCCQ relaive o VSS -0.3 VCCQ +0.3 V Volage on VCC supply relaive o VSS V Volage on VCCQ supply relaive o VSS V Sresses greaer han hose lised may cause permanen damage o he device. This is a sress raing only, and funcional operaion of he device a hese or any oher condiions above hose indicaed in he operaional secions of his specificaion is no implied. Exposure o absolue maximum raing condiions for exended periods may affec reliabiliy. 9.2 Elecrical Characerisics and Operaing Condiions Descripion Condiions Symbol Min Max Uni Noe Supply volage VCC V I/O supply volage VCCQ V Inpu high volage VCCQ 0.4 VCCQ+0.2 V 1 Inpu low volage V 2 Oupu high volage IOH= 0.2mA VOH 0.8xVCCQ V 3 Oupu low volage IOL=+0.2mA VOL 0.2xVCCQ V 3 Inpu leakage curren VIN=0 ovccq ILI 1 μa Oupu leakage curren OE#= or chip disabled ILO 1 μa OPERATING CURRENT Asynchronous random READ/WRITE Iniial access, burs READ/WRITE Coninuous burs READ Coninuous burs WRITE VIN = VCCQ or 0V chip enabled, IOUT=0 ICC1 RC/WC=70ns - 25 ma 4 ICC2 ICC3R ICC3W 133MHz MHz MHz MHz MHz MHz - 35 ma 4 ma 4 ma 4 Sandby Curren VIN = VCCQ or 0V, CE# = VCCQ ISB Sandard ua 5,6 Noes: 1. Inpu signals may overshoo o VCCQ + 1.0V for periods less han 2ns during ransiions. 2. Inpu signals may undershoo o VSS 1.0V for periods less han 2ns during ransiions. 3. BCR[5:4] = 01b (defaul seing of one-half drive srengh). 4.This parameer is specified wih he oupus disabled o avoid exernal loading effecs. The user mus add he curren required o drive oupu capaciance expeced in he acual sysem. 5.ISB (max) values measured wih PAR se o FULL ARRAY and a +85 C. In order o achieve low sandby curren, all inpus mus be driven o eiher VCCQ or VSS. ISB migh be slighly higher for up o 500ms afer power-up, or when enering sandby mode. Publicaion Release Dae : June 27, Revision : A01-003

33 9.3 Deep Power-Down Specificaions 256Mb Async./Burs/Sync./A/D MUX DESCRIPTION CONDITIONS SYMBOL TYPICAL UNIT Deep Power- VIN = VCCQ or 0V; IZZ 10 μa Down VCC, VCCQ = 1.95V; +85 C Noe: Typical (TYP) IZZ value applies across all operaing emperaures and volages. 9.3 Parial Array Self Refresh Sandby Curren Descripion Condiions Symbol Parial-array refresh Sandby curren VIN = VCCQ or 0V, CE# = VCCQ IPAR Sandard power (no designaion) Array Pariion Max Full / / / Uni ua 9.4 Capaciance Descripion Condiions Symbol Min Max Uni Noe Inpu Capaciance CIN pf 1 TC = +25ºC; f = 1 MHz; VIN = Inpu/Oupu 0V CIO pf 1 Capaciance (A/DQ) Noes: 1. These parameers are verified in device characerizaion and are no 100% esed. 9.5 AC Inpu-Oupu Reference Wave form VccQ Inpu 1 VccQ/2 2 Tes Poins VccQ/2 3 Oupu VssQ Noes:1.AC es inpus are driven a VCCQ for a logic 1 and VSSQ for a logic 0. Inpu rise and fall imes (10% o 90%) <1.6ns. 2.Inpu iming begins a VCCQ/2. 3.Oupu iming ends a VCCQ/ AC Oupu Load Circui Tes Poin 50 Ohm DUT VCCQ/2 30pF Noes: All ess are performed wih he oupus configured for defaul seing of half drive srengh (BCR[5:4] = 01b). Publicaion Release Dae : June 27, Revision : A01-003

34 256Mb Async./Burs/Sync./A/D MUX 10. TIMING REQUIRMENTS 10.1 Read, Wrie Timing Requiremens Asynchronous READ Cycle Timing Requiremens All ess performed wih oupus configured for defaul seing of half drive srengh, (BCR[5:4] = 01b). Parameer Symbol Min Max Uni Noe Address access ime AA 70 ns ADV# access ime AADV 70 ns Address hold from ADV# HIGH AVH 2 ns Address seup o ADV# HIGH AVS 5 ns LB#/UB# access ime BA 70 ns LB#/UB# disable o DQ High-Z Oupu BHZ 7 ns 1 Chip selec access ime CO 70 ns CE# LOW o ADV# HIGH CVS 7 ns Chip disable o DQ and WAIT High-Z oupu HZ 7 ns 1 Oupu enable o valid oupu OE 20 ns OE# LOW o WAIT valid OEW ns Oupu disable o DQ High-Z oupu OHZ 7 ns 1 Oupu enable o Low-Z oupu OLZ 3 ns 2 ADV# pulse widh VP 5 ns Noes: 1. Low-Z o High-Z imings are esed wih AC Oupu Load Circui. The High-Z imings measure a 100mV ransiion from eiher VOH or VOL oward VCCQ/2. 2. High-Z o Low-Z imings are esed wih he circui. The Low-Z imings measure a 100mV ransiion away from he High-Z (VCCQ/2) level oward eiher VOH or VOL. Publicaion Release Dae : June 27, Revision : A01-003