Buffering High-Speed Packets with Tri-Stage Memory Array and Its Performance Analysis

Transcription

1 /2005/6(2) Journal of Software Vol6, No2,2+, 2,, (,00084) 2 (, ) Bufferng Hgh-Speed Packets wth Tr-Stage Memory Array and Its Performance Analyss WANG Peng,2+, YI Peng 2, JIN De-Peng, ZENG Le-Guang (Department of Electronc and Engneerng, Tsnghua Unversty, Bejng 00084, Chna) 2 (Department of Electronc and Engneerng, Informaton Engneerng Unversty, Zhengzhou , Chna) + Correspondng author: Phn: , E-mal: wang-p0@malstsnghuaeducn, Receved ; Accepted Wang P, Y P, Jn DP, Zeng LG Bufferng hgh-speed packets wth tr-stage memory array and ts performance analyss Journal of Software, 2005,6(2): DOI: 0360/jos628 Abstract: Hgh-Performance routers and swtches need large throughput packet buffers to hold packets However, the technque of commercally avalable memores s lmted and can hardly fulfll ths hgh throughput packet buffers As a result, the development of networks s restrcted severely Ths paper presents a tr-stage memory array archtecture to solve the problem, whch can accomplsh the arbtrary hgh-speed packet buffer theoretcally It s proved that the crtcal queue frst algorthm can be appled as the memory management algorthm to get zero delay schedulng as well as mnmum scale system Furthermore, the desgn of hardware mplementaton archtecture of the tr-stage memory array system s provded fnally Key words: tr-stage memory array; packet buffer; delay :,,,,, : ; : TP302 : A Supported by the Natonal Hgh-Tech Research and Development Plan of Chna under Grant No200AA207 ( (863)) : (976 ),,,,, ; (977 ),,, ; (972 ),,,, ; (947 ),,,,

2 282 Journal of Software 2005,6(2), [,2] 60Gbt/s, 64bt, 04ns N, 04/N ns, 8, 6,, [4] [5] [6],, [7 9] Stanford Sundar Iyer DRAM SRAM, (SRAM DRAM) [2,9,0],, SRAM SRAM, SRAM DRAM SRAM, DRAM, [2,9,0],,,,,, : (), ( ) DRAM 30ns, SRAM 3ns, 60Gbt/s [] (2), ( ), RTT Rbt( RTT(round trp tme),r ) Internet RTT 200ms ~300ms, 60Gbt/s, 40Gbt DRAM Gbt/,SRAM 6Mbt/,,DRAM (3) FIFO( ) (VO) [2], FIFO [3],, OC92, 256K (4) [2],,, ((3) (4)), [2,3] Gordon Moore 995, ( ), Gordon Moore ( 975 ~996 ), 8,,, [2,9,0], / / /, 0

3 : 283 2, 3,, DRAM FIFO Input stage Mddle stage Output stage Arrvng packets Outgong packets R R Input scheduler Output scheduler Fg Tr-Stage memory array,,,,, : R T R( / ), B T DRAM, b = B DRAM ( ): T/b, T b DRAM (cell): R T, R( / ), ( b,, ) : :DRAM T, DRAM b DRAM b, b DRAM : DRAM T, b DRAM,, DRAM ( DRAM ), R( / ) Stanford SRAM DRAM, :,

4 284 Journal of Software 2005,6(2) ( ), 0 2 : b DRAM b ( R) B, T b DRAM, b DRAM, b b DRAM, 2, k b : DRAM, DRAM, DRAM DRAM,b b,, R( / ), b, b b DRAM, R( / ) Mddle stage Output stage k DRAM j k DRAM 2 j 2 Outgong packets k DRAM b j q k q q j q Output scheduler Fg2 Mddle stage and output stage 2,,, (underrun) [2,9,0] 3, : O(,: t, ; U(,: t, (, ); ( ), ( ), (b )(2+ln)+2b DRAM

5 : 285 : ~ ~,, /b, ( /b) U(,)=, + (2 /b), U(,)= 2, ( /b)b, ( /b) 2 U(,(2 /b))=2, x ( /b) x U(,b( ( (/b) x )))=x, ( /b) x =, x=(ln)/(ln(b/b )) ln(+x)<x, ln(b/(b ))</(b ), x>(b )ln, (b )ln, (b )ln, U(, (b )ln,, (b )(+ln),, (b )(+ln), b (b )(2+ln), DRAM 2b, 2b DRAM (b )(2+ln)+2b DRAM :, b U(, ( U(,, ) : b ; 2: b DRAM DRAM, v(=(v,v 2,,v ) ~ U(, t f (, v(, F(),, f(, F()=max{ t τ,f(,}(τ ), F() (b )+b :, : U(,, U(,<b, =, U(,=b, U (, U(, U(,=0,, U (, = U (, ( ) t U(,=b, b, U(, b, U (, F() F() (b )+b 2 + 2, F ( ) < + ln( ) :, t F(),,U(,t b) F() b(, U(,<F() F()), j t b, = k= = U(j,t b) U(,t b) F() b () F(2) F(2,t b)=u(,t b)+u(j,t b) (2) F(2) F() b+f() b (3) =

6 286 Journal of Software 2005,6(2) (5) =0, (6) F(2) b F(3) F(2) b + 2 (4) F( ) b F( + ) F( ) b + (5) F () ( b ) + b + b (6), N = = N > < + ln( N ) (7) 2 + F ( ) < b + ln( ) 3, F ( ) 2b + b : (5),, (7) > ln( ) j j= j= + bln,2 + + F ( ) b b b (8) k= k =, {2,, } j j j j= j= F ( ) 2b + b + bln, {2,3,, } 2( ),,, b(3++ln( )) 2 DRAM, b(2++ln( )) DRAM : 2, b(2++ln( )) DRAM U(, t 2 +, b + ln( ), F(), t+b b, 3 + b + ln( ) 2, b(3++ln( )) 2 F() U(,, b(2++ln( )) 3( ) F() ( ): α = U (, F() F ) = max α α ( Uα = (9), t α Fα() 0 ~t (a,a 2,,a k ) k α,, U α (,, α τ, (,

7 : 287, U (, τ ) U (, τ ) = = α, U (, τ ) > Uα (,τ ), Fα F(), F() = = F(), DRAM : [0], [0], [0] SRAM, [0] SRAM (, SRAM 0), 4,, 60Gbt/s, 256bt 30ns DRAM, b(3++ln( )) 2 DRAM =256k(OC92, ), DRAM ( ),, 4 DRAM, DRAM ( ), 3 Mddle stage 2 Output stage Block 0 Block Outgong packets b Cell Cell buffer 3b Cell 3b Cell Subblock Subblock 2 Cell Cell Output scheduler Block 2 Cell buffer 2 3b Cell Subblock b Cell Fg3 Revsed output stage archtecture Fg4 Block archtecture n revsed output stage 3 4 3, 4, 2 b, b b 2b DRAM, 2b 3b b(3 + + ln( )) 2 3b DRAM, 3b, 2b 2b

8 288 Journal of Software 2005,6(2) b b,,, : 0~ b,, 2 0 : b~ 2b, 2, 3 b : 2b~ 3b, 3, 2b, b (+)b, mod 3, b (+) mod 3 DRAM b,, (, ( ) 3b 3b, DRAM, (2b+3b 2 ) DRAM, DRAM, DRAM 42,DRAM, SRAM, DRAM SRAM, B bt SRAM, Ts (Ts<T), Rbt/s, R Ts a = SRAM SRAM, a(a<b) B, a,, 3, 4, a 3b b(3 + + ln( )) 2 3b SRAM, (2b+3ab) 3 SRAM, SRAM 3ns, a=2, 456 SRAM, DRAM, a<b,, [4],,, Name Table Zero-Delay packet access Performance comparsons between currently avalable memory archtectures Bounded-Delay packet access Implementaton scale and Bufferng speed complexty surpasses the bandwdth (The number of memory blocks of memory n need) Support large volume bufferng Commonly used archtectures n Not support Not support Partly support Medum Partly support computers PPB [3,8] Support Support Support () Support(but dffcul Hybrd Not support (lmted by SRAM DRAM Support Support ((b )+ tme slots) the throughput of 6(2b+3ab)+ ( R RTT) archtecture [9,0] V SRAM) DRAM Support Support (can acheve Tr-Stage ( R RTT) Support Support ((b )+b+ tme slots) arbtrary hgh-speed + Memory Array V theoretcally) DRAM Support : [3,8,9,0],,,, DRAM b( ln( )) 2 bt, 3b b( ln( )) 2, 3b, 3b

9 : 289, PPB ( ),,, DRAM,, VDRAM DRAM, R RTT DRAM 56% V DRAM, Xlnx FPGA xc2v3000(300 ), 5,,,,,, References: [] Shah D, Iyer S, Prabhakar B, McKeown N Mantanng statstcs counters n router lne cards IEEE Mcro, 2002,22():76 8 [2] Iyer S, Kompella RR, McKeown N Technques for fast packet buffers yer-presentatonpdf [3] Salesh K, Venkatesh R, Phlp J, Shukla S Implementng parallel packet bufferng: Part story/oeg s0006 [4] Alexander T, Kedem G Dstrbuted prefetch-buffer/cache desgn for hgh performance memory systems In Proc of the 2nd Int l Symp on Hgh-Performance Computer Archtecture Pscataway: IEEE Press, [5] Rxner S, Dally WJ, Kapas UJ, Mattson P, Owens JD Memory access schedulng In: Proc of the 27th Annual Int l Symp on Computer Archtecture IEEE/ACM Press, [6] Broder A, Mtzenmacher M Usng multple hash functons to mprove IP lookups In: Proc of the IEEE INFOCOM 200 IEEE Press, [7] Joo Y, McKeown N Doublng memory bandwdth for network buffers In: Proc of the IEEE Infocom Vol2, IEEE Press, [8] Salesh K, Venkatesh R, Phlp J, Shukla S Implementng parallel packet bufferng: Part story/oeg s00068 [9] Iyer S, Kompella RR, McKeown N Analyss of a memory archtecture for fast packet buffers In: IEEE Hgh Performance Swtchng and Routng [0] Iyer S, Kompella RR, McKeown N Desgnng buffers for router lne cards [] Shor M, L K, Walpole J Applcaton of control theory to modelng and analyss of computer systems In: Proc of the Japan-USA-Vetnam Work shop on Research and Educaton n Systems Hochmnh Cty: RESCCE Press, [2] McKeown N The SLIP schedulng algorthm for nput-queued swtches IEEE Trans on Networkng, 999,7(4):88 20 [3] Bhagwan R, Ln B Fast and scalable prorty queue archtecture for hgh-speed network swtches In: Proc of IEEE INFOCOM 2000 IEEE Press, [4] Wang P, DP Jn, Zeng LG Analyss of a tr-stage memory array for hgh-speed packet buffers In: Proc of the SPIE, Vol