Ptolemy II in Embedded Signal Processing Architectures: Deriving Process Networks From Matlab

Transcription

1 Ptolemy II n Embedded Sgnal Processng Archtectures: Dervng Process Networs From Matlab Bart Kenhus and Ed Deprettere Leden Insttute of Advanced omputer Scence (LIAS) Leden Unversty, The Netherlands Ptolemy Mn-conference. Bereley, March / Applcaton for = ::K, fo rj r j= = ::N, :N, [r(j,j), x(,j), t] = Vec( r(j,j), x(,j) ); for r = j+ : ::N, :N, [r(j,), x(,), t] = R ot( r(j,), x(,), t); een n d e ene nd Mappng? Problem Polyhedra Reduced Depence Graph MatParser DGParser Panda Programmable Interconnect Networ Memory PE PE PE... PEn Mcro Processor Archtecture SPADE Process Networ

2 ompaan Matlab Process Generaton n more detal Step. MatParser reduced depence graph Step. Step. sngle assgnment code DgParser polyhedral reduced depence graph Panda process networ Step n more detal polyhedral reduced depence graph Networ generaton networ descrpton Process generaton SBF objects doman scannng lnearzaton data doman parttonng reconstructon SBF objects for =::K, for j=::n, [r(j,j),x(,j),t]=vec(r(j,j),x(,j)); for =j+::n, [r(j,),x(,),t]=rot(r(j,),x(,),t)); N Step : MatParser ->= Array Dataflow Analyss r_(-,j) for = : : K, for j = : : N, f ->=, [ n_ ] = pd( r_( -, j ) ); else %% f -+ >= [ n_ ] = pd( r_( j, j ) ); [ out_,out_,out_ ] = Vec( n_, n_ ); j r_(j,j) [ r_(, j) ] = ( out_ ); [ x_(, j) ] = ( out_ ); [ t_(, j) ] = ( out_ ); for =j+::n, K

3 Depence Graph for = ::K, fo rj r j= = ::N, :N, [r(j,j), x(,j), t] = Vec( r(j,j), x(,j) ); for = j+ ::N, [r(j,), x(,), t] = R oot( r(j,), x(,), t t); een n d d en d Depence Graph j Vec Rot 5 Step : DgParser e A a b c f g E l B d D h j Polyhedral Reduced Depence Graph

4 Example of Node and Port Domans 7 Step : PANDA Producer FIFO buffer onsumer M() Doman Reconstructon Doman Scannng Lnearzaton 8

5 pd pd pd PN Model n Ptolemy II /** fre the actor. */ publc vod fre() throws IllegalActonExcepton { for ( nt = ; <= *K ; += ) { for ( nt j = ; j <= *N ; j += ) { f ( - >= ) { n_ = RP_.get(); } f ( - == ) { n_ =RP_.get(); } f ( j - >= ) { n_ = RP_.get(); } f ( j - == ) { n_ = RP_.get(); } // Execute the functon [out_, out_, out_] = F.Vectorze(n_, n_); pd Port Domans } } } f ( K - - >= ) { WP_.s( out_ ); } f ( -K + == ) { WP_.s( out_ ); } f ( N - j - >= ) { WP_.s( out_ ); } 9 Ptolemy II, Smulaton Early Exploraton 5

6 Worload Analyss e 59 A b 5 a Antenna s Updates c f 5 g 5 l 5 E B d 5 D h 5 h 85 j j Separaton ommuncaton/omputaton Hgher levels of granularty Exploraton of Possble Archtectures InterD output InterBD InterD nput InterB Bc Bd c g f Dd Df Dg oprocessor B E H I oprocessor oprocessor D Mcroprocessor (A/E) a Dl Db Aa Ab El E Spade Envronment McroProcessor/oprocessor Bus

7 FPGA Hardware Realzaton Xllnx Vrtex E ompaan secs ) Synthess usng Synplcty Synplfy - mnutes ) Place and Route usng Xlnx Desgn Manager - mnutes In cooperaton wth DERA, Farnborough, Unted Kngdom Y-chart Worload Analyss Early ntegraton Hgh-level abstracton Applcaton n Matlab ompaan Fast evaluatons Valdaton Level Archtecture Mappng Process Networ Ptolemy II PN Doman Valdaton Level Spade Valdaton Y-chart Envronment Performance Numbers Ptolemy II serves as the ntegraton envronment FPGA/DSP Level 7