Resource Efficient Design and Implementation of Standard and Truncated Multipliers using FPGAs

Transcription

1 Proceedngs of the World Congress on Engneerng 2011 Vol II, July 6-8, 2011, London, U.K. Resource Effcent Desgn and Implementaton of Standard and Truncated Multplers usng FPGAs Muhammad H. Ras, Member, IAENG, Mohamed H. Al Mjall, and Mohammad Nsar Abstract We study the Feld Programmable Gate Array (FPGA) mplementaton of fxed wdth standard and truncated multplers usng Very Hgh speed ntegrated crcut Hardware Descrpton Language and mplemented on Spartan-3AN, Vrtex and Vrtex-E devces. We have acheved remarkable reducton n FPGA resources, power and delay when the full precson of standard multpler s not requred and the truncated multpler can be mplemented wth fewer resources. The comparsons of dfferent FPGA devces layout show that the standard multplers utlze lot of space as compared to truncated multplers whch could be utlzed for other embedded resources. Index Terms DSP, Spartan-3AN, Truncated Multpler, Vrtex, Vrtex-E, VHDL. M I. INTRODUCTION ULTIPLICATION requres ntensve and tedous scentfc computatons for sgnal processng (DSP) applcatons [1-3]. For the mplementaton of DSP algorthm demands usng Applcaton Specfc Integrated Crcuts (ASICs), whch s especally requred for mage processng applcatons such as JPEG and MPEG etc. Due to hgh development costs for ASICs, algorthms should be verfed and optmzed before mplementaton [4]. The current development n very large scale ntegraton (VLSI) technology, hardware mplementaton has become a desrable alternatve. Feld programmable gate arrays (FPGAs) have become known as a platform of choce for effcent hardware mplementaton of computaton ntensve algorthms [5]. FPGAs enable a hgh degree of parallelsm and can acheve orders of magntude speedup over general purpose processors (GPPs). Ths s entrely due to many embedded resources avalable and beneft of hardware speed and the flexblty of software n FPGA. Ths makes FPGA a Manuscrpt receved Aprl 16, Ths work was supported n part by Cornea Research Char, the College of Appled Medcal Scences, Kng Saud Unversty. M. H. Ras s wth the Cornea Research Char, College of Appled Medcal Scences, Kng Saud Unversty, Ryadh 11433, Saud Araba (phone: ; fax: ; (e-mal: mhras@yahoo.com.au). M. H. Al Mjall s wth the Bomedcal Technology Department, College of Appled Medcal Scences, Kng Saud Unversty, Ryadh 11433, Saud Araba (e-mal: almjall@yahoo.com). M. Nsar s wth the Bomedcal Technology Department, College of Appled Medcal Scences, Kng Saud Unversty, Ryadh 11433, Saud Araba (e-mal: m_nsar@yahoo.com). vable technology and an attractve alternatve to ASICs [5-6]. DSP, mage processng and multmeda applcatons extensvely requres multplcaton and squarng functons [7-8]. A full wdth dgtal n n multpler computes the 2n output as a weghted sum of partal products [9]. If the product s truncated to n-bts, the least-sgnfcant columns of the product matrx contrbute lttle to the fnal result. To take advantage of ths, truncated multplers and squarers do not form all of the least-sgnfcant columns n the partal-product matrx [10]. As more columns are elmnated, the area and power consumpton of the arthmetc unt are sgnfcantly reduced, and n many cases the delay also decreases. The trade-off s that truncatng the multpler matrx ntroduces addtonal error nto the computaton. Cryptography requres not only a sgnfcant number of multplcaton and squarng functons but also large ntegers [11-12]. Many research efforts have been presented n lterature to acheve hardware effcent mplementaton of a truncated multpler. The basc dea of these technques s to dscard some of the less sgnfcant partal products and to ntroduce a compensaton crcut that partly compensates for the dropped terms, thereby reducng approxmaton error [13-18]. In reference [19] presented a truncated multpler wth mnmum square error for every nputs bt wdth. By parallel processng and ppelnng a hgh speed multplcaton can be acheved for DSP applcatons, ths could be made more effcent by ntroducng truncated multplcaton. Ras has presented a study on standard and truncated multplers usng FPGA devces [20-22]. Babc et al. [23] recently publshed a new approach to mprove the accuracy and effcency of Mtchell s algorthm based multplcaton. The rest of ths paper s structured as follows. In secton II, descrbes the mathematcal bass of truncated multplcaton. Secton III addresses the archtectural platform used n ths study. Secton IV presents the FPGA desgn and mplementaton results. Fnally, secton V presents the concluson. II. MATHEMATICAL BASIS OF TRUNCATED MULTIPLIERS Consderng the multplcaton of two n-bt nputs X and Y, a standard multpler performs the followng operatons to obtan the 2n bt product P ISSN: (Prnt); ISSN: (Onlne)

2 Proceedngs of the World Congress on Engneerng 2011 Vol II, July 6-8, 2011, London, U.K. 2n1 n1 n1 P XY P 2 ( x 2 )( y 2 ) (1) where x, y and P represent the th bt of X, Y and P, respectvely. Fg. 1 shows the standard archtecture of -bt parallel multpler, where HA and FA are the half and full adders respectvely. Equaton (1) can be expressed by the sum of two segments: the most-sgnfcant part MP and the least-sgnfcant part LP of fve fundamental programmable functonal elements: CLBs,, Block RAMs, dedcated multplers (18 18) and dgtal clock managers (DCMs), Spartan-3 famly ncludes Spartan-3L, Spartan-3E, Spartan-3A, 2n1 n1 MP LP P 2 P (2) 0 0 P 2 The standard -bt parallel multpler can also be dvded nto three subsets: the most-sgnfcant part MP, nput correcton IC and the least-sgnfcant part LP. Equaton (2) can be rewrtten as follows: P MP IC LP (3) The fxed wdth multpler can be obtaned drectly by removng the LP regon and ntroducng the IC regon to obtan MP regon, whch s truncated multpler as shown n Fg. 2 and gven by equaton (4). P MP IC (4) III. ARCHITECTURE PLATFORM Due to the parallel nature, hgh frequency, and hgh densty of modern FPGAs, they make an deal platform for the mplementaton of computatonally ntensve and massvely parallel archtecture. In ths secton a bref ntroducton about state-of-the-art FPGAs from Xlnx s presented. Fg. 1. The archtecture of a standard -bt parallel multpler A. Spartan-3 FPGAs The Spartan-3 FPGA belongs to the ffth generaton Xlnx famly. It s specfcally desgned to meet the needs of hgh volume, low unt cost electronc systems. The famly conssts of eght member offerng denstes rangng from 50,000 to fve mllon system gates [24]. The Spartan-3 FPGA conssts Fg. 2. The archtecture of a truncated -bt parallel multpler Spartan-3A DSP, Spartan-3AN and the extended Spartan-3A FPGAs. Partcularly, the Spartan-3AN s used as a target technology n ths paper. Spartan-3AN combnes all the feature of Spartan-3A FPGA famly plus leadng technology n-system flash memory for confguraton and nonvolatle data storage. B. Vrtex FPGAs Vrtex devces feature a flexble, regular archtecture that comprses an array of confgurable logc blocks (CLBs) surrounded by programmable nput/output blocks (), all nterconnected by a rch herarchy of fast, versatle routng resources. The Vrtex famly comprses of nne members offerng denstes rangng from 57,906 to 1,124,022 system gates [25]. The abundance of routng resources permts the Vrtex famly to accommodate even the largest and most complex desgns. Vrtex FPGAs are SRAM-based, and are customzed by loadng confguraton data nto nternal memory cells. In some modes, the FPGA reads ts own confguraton data from an external PROM (master seral mode). Vrtex devces provde better performance than prevous generatons of FPGA. Desgns can acheve synchronous system clock rates up to 200 MHz ncludng I/O. C. Vrtex-E FPGAs The Vrtex-E FPGA famly delvers hgh-performance hgh-capacty programmable logc solutons. The Vrtex-E famly offers up to 43,200 logc cells n devces up to 30% faster than the Vrtex famly. The Vrtex-E famly delvers a hgh-speed and hgh-capacty programmable logc soluton. The Vrtex-E famly comprses the eleven members offerng denstes rangng from 71,693 to 4,074,387 system gates [26]. Vrtex-E devces have up to 640 Kb of faster (250 MHz) block SelectRAM, but the ndvdual RAMs are the same sze and structure as n the Vrtex famly. They also have eght ISSN: (Prnt); ISSN: (Onlne)

3 Proceedngs of the World Congress on Engneerng 2011 Vol II, July 6-8, 2011, London, U.K. DLLs nstead of the four n Vrtex devces. Each ndvdual DLL s slghtly mproved wth easer clock mrrorng and 4x frequency multplcaton. The Vrtex-E devces bult aggressve 6-layer metal 0.18 µm CMOS process. Vrtex-E devces feature a flexble, regular archtecture that comprses an array of confgurable logc blocks (CLBs) surrounded by programmable nput/output blocks (), all nterconnected by a rch herarchy of fast, versatle routng resources. Vrtex-E FPGAs are SRAM-based, and are customzed by loadng confguraton data nto nternal memory cells. Vrtex-E devces provde better performance than prevous generatons of FPGAs. Desgns can acheve synchronous system clock rates up to 240 MHz ncludng I/O or 622 Mb/s usng Source Synchronous data transmsson archtectures. IV. FPGA DESIGN AND IMPLEMENTATION RESULTS The desgn of standard and truncated,,, and -bt multplers are done usng VHDL and mplemented n a Xlnx Spartan-3AN XC3S700AN (package: fgg484, speed grade: -5), Vrtex XCV50 (package: fg256, speed grade: -6) and Vrtex-E XCV50E (package: fg256, speed grade: -8) FPGA usng the Xlnx ISE 9.2 desgn tool [27]. FPGA layouts of the standard,,, and -bt multplers are shown n Fgs. 3, 4, 5 and 6. FPGA layouts of truncated,,, and -bt multplers are further shown n Fgs. 7, 8, 9 and 10. The FPGA layouts shown n Fgs. 3, 4, 5, 6, 7, 8, 9 and 10 of standard and truncated,,, and -bt multplers also show less utlzaton of FPGA area for truncated multpler, whch s an ndcaton of best utlzaton of the FPGA resources. Tables 1, 2 and 3 summarze the FPGA devce resources utlzaton for standard and truncated,,, and -bt multplers. Table 4 presents the percentage change between the standard to truncated,,, and -bt multplers, whch clearly demonstrates that the occuped slces ranges from 145% to 170% for Spartan-3AN, Vrtex and Vrtex-E FPGA devces. The reducton n pn delay and the number of occuped slces used n truncated multpler also show that t s one of the vable solutons for mage processng applcatons, where most of the redundant nformaton can be removed. better FPGA devce than other Vrtex and Vrtex-E FPGAs. The comparson of FPGA layouts of standard and truncated multplers also demonstrates that the less area s utlzed for the resources and the remanng could be utlzed for other embedded resources. Fg. 3. FPGA layout of standard -bt multpler Fg. 4. FPGA layout of standard -bt multpler Fg. 5. FPGA layout of standard -bt multpler V. CONCLUSION In ths paper we have presented hardware desgn and mplementaton of FPGA based parallel archtecture for standard and truncated multplers utlzng VHDL. The desgn was mplemented on Xlnx Spartan-3AN XC3S700AN, Vrtex XCV50 and Vrtex-E XCV50E FPGA devces usng the ISE 9.2 desgn tool. The objectve s to present a comparatve study of the,,, and -bt standard and truncated multplers usng FPGA devces. The comparson between standard and truncated multpler show much more reducton n devce utlzaton. The FPGA devces used almost same number of occuped slces but ther average connecton and maxmum pn delays are dfferent; whch clearly ndcates that the Spartan-3AN s Fg. 6. FPGA layout of standard -bt multpler ISSN: (Prnt); ISSN: (Onlne)

4 Proceedngs of the World Congress on Engneerng 2011 Vol II, July 6-8, 2011, London, U.K. Fg. 7. FPGA layout of truncated -bt multpler Fg. 8. FPGA layout of truncated -bt multpler Fg. 9. FPGA layout of truncated -bt multpler Fg. 10. FPGA layout of truncated -bt multpler REFERENCES [1] L.V. Agostn, I.S. Slva, S. Bamp, Multplerless and fully ppelned JPEG compresson soft IP targetng FPGAs, Mcroprocessors & Mcrosystems, vol. 31 no. (8), pp , [2] V. Gerenz, C. Pans, J. Nurm, Parameterzed MAC unt generaton for a scalable embedded DSP core, Mcroprocessors & Mcrosystems, vol. 34 no. (5), pp , [3] M.Y. Kong, J.M.P. Langlos, D. Al-Khall, Effcent FPGA mplementaton of complex multplers usng the logarthmc number system, n proc. of IEEE Internatonal Symposum on Crcuts and Systems, pp , [4] A. Zemva, M. Verderber, FPGA-orented HW/SW mplementaton of the MPEG-4 vdeo decoder, Mcroprocessors & Mcrosystems, vol. 31 no. (5), pp , [5] T.J. Todman, G.A. Constantndes, S.J.E. Wlton, O. Mencer, W. Luk, P.Y.K. Cheung, Reconfgurable computng: archtectures and desgn methods, n proc. of IEE nternatonal conference on Computer Dgtal Technques, vol. 152, no. (2), pp , [6] C. Maxfeld, The Desgn Warror s Gude to FPGAs: Devces, Tools and flows, Newnes Publshers, MA, [7] E.III. Walters, M.G. Arnold, M.J. Schulte, Usng truncated multplers n DCT and IDCT hardware accelerators, n Proc. of the XIII SPIE Advanced Sgnal Processng Algorthms, Archtectures, and Implementatons, pp , [8] J. A. Kalomros, J. Lygouras, Desgn and evaluaton of a hardware/software FPGA-based system for fast mage processng, Mcroprocessors & Mcrosystems, vol. 32 no. (2), pp , [9] C.R. Baugh, B.A. Wooley, A Two s Complement Parallel Array Multplcaton Algorthm, IEEE Trans. Comput. Vol. C-22, no.12, pp , [10] E.E. Swartzlander Jr., Truncated Multplcaton wth Approxmate Roundng, n Proc. of the 33rd Aslomar Conference on Sgnals, Systems and Computers. Vol. 2, pp , [11] W. Stallngs, Cryptography and Network Securty: Prncples and Practces, Prentce-Hall, 4th edn., Upper Saddle Rver, NJ, [12] M.-H. Jng, Z.-H. Chen, J.-H. Chen, Y.-H. Chen, Reconfgurable system for hgh-speed and dversfed AES usng FPGA, Mcroprocessors & Mcrosystems, vol. 31 no. (2), pp , [13] S.S. Kdamb, F.El-. Gubaly, A. Antonous, Area-Effcent Multplers for Dgtal Sgnal Processng Applcatons, IEEE Trans. Crcuts and Systems-II: Analog and Dgtal Sgnal Processng, vol. 43, no. 2, pp , [14] Y.C. Lm, Sngle-Precson Multpler wth Reduced Crcut Complexty for Sgnal Processng Applcatons, IEEE Trans. Comput. Vol. 41, no. 10, pp , [15] J.M. Jou, S.R. Kuang R.D. Chen, Desgn of Low-Error Fxed-Wdth Multplers for DSP Applcatons, IEEE Trans. Crcuts and Systems-II: Analog and Dgtal Sgnal Processng, vol. 46, no. 6, pp [16] L. Van, S. Wang, W. Feng, Desgn of the Lower Error Fxed-Wdth Multpler and Its Applcaton, IEEE Trans. Crcuts and Systems-II: Analog and Dgtal Sgnal Processng, vol. 47, no. 10, [17] S.R. Kuang, J.P. Wang, Low-error confgurable truncated multplers for multply-accumulate applcatons, Elect. Lett. Vol. 42, no. 16, pp , [18] Van, L-D. and C-C.Yang, Generalzed low-error area-effcent fxed-wdth multplers, IEEE Transactons Crcuts and Systems I, Regular Paper. vol. 52 no. (8). pp [19] V. Garofalo, N. Petra, D. DeCaro, A.G.M. Strollo, E. Napol, Low error truncated multplers for DSP applcatons, n Proc. of the 15th IEEE Internatonal Conference on Electroncs, Crcuts and Systems, pp , [20] M.H. Ras, FPGA desgn and mplementaton of fxed wdth standard and truncated -bt multplers: A comparatve study, n Proc. of the 4th IEEE Internatonal Desgn and Test Workshop, IEEE Xplore Press, pp. 1-4, [21] M.H. Ras, Effcent hardware realzaton of truncated multplers usng FPGA, Int., J. of Appled Scence, Engneerng and Technology, vol. 5, no. 2, pp , [22] M.H. Ras, Hardware mplementaton of truncated multplers usng Spartan 3AN, Vrtex-4 and Vrtex-5 devces, Amercan J. of Engneerng and Appled Scences, vol. 3, no. 1, pp , [23] Z. Babc, A. Avramovc, P. Bulc, An teratve logarthmc multpler, Mcroprocessors & Mcrosystems, vol. 35, pp , [24] Xlnx, Spartan-3 FPGA famly datasheet, (2009). [25] Xlnx, Vrtex FPGA famly datasheet, (2001). [26] Xlnx, Vrtex-E FPGA famly datasheet, (2002). [27] Xlnx, ISE 9.2 desgn tool, (2007) ISSN: (Prnt); ISSN: (Onlne)

5 Proceedngs of the World Congress on Engneerng 2011 Vol II, July 6-8, 2011, London, U.K. Bt Wdth TABLE I FPGA RESOURCE UTILIZATION FOR STANDARD AND TRUNCATED MULTIPLIER FOR SPARTAN-3AN XC3S700AN (PACKAGE:FGG484, SPEED GRADE:-5) Multplers Occuped Slces Equvalent Connecton Maxmum Pn Standard Truncated Standard Truncated Standard Truncated Standard Truncated Bt Wdth Bt Wdth Multplers TABLE II FPGA RESOURCE UTILIZATION FOR STANDARD AND TRUNCATED MULTIPLIER FOR VIRTEX XCV50 (PACKAGE:FG256, SPEED GRADE:-6) Occuped Slces Equvalent Connecton Maxmum Pn Standard Truncated Standard Truncated Standard Truncated Standard Truncated TABLE III FPGA RESOURCE UTILIZATION FOR STANDARD AND TRUNCATED MULTIPLIER FOR VIRTEX-E XCV50E (PACKAGE:FG256, SPEED GRADE:-8) Multplers Occuped Slces Equvalent Connecton Maxmum Pn Standard Truncated Standard Truncated Standard Truncated Standard Truncated TABLE IV PERCENTAGE CHANGE BETWEEN THE STANDARD AND TRUNCATED MULTIPLIER FOR SPARTAN-3AN, VIRTEX AND VIRTEX-E FPGA DEVICES BIT WIDTH (MULTIPLIERS) Occuped Slces Equvalent (Standard/Truncated) 166.7% 145.4% 162.2% (Standard/Truncated) 155.8% 150% 154% (Standard/Truncated) 159.2% 155% 159.2% (Standard/Truncate) 176.2% 170.1% 176.2% ISSN: (Prnt); ISSN: (Onlne)