The State of Open Source Processors and Open Source Silicon. Stefan Tensilica Day LibreCores. Free and Open Digital Hardware
|
|
|
- Angel Hines
- 6 years ago
- Views:
Transcription
1 The State of Open Source Processors and Open Source Silicon Stefan Tensilica Day 2017 LibreCores Free and Open Digital Hardware
2 Karen Arnold, CC0 2
3 Open Source Processors vs. ISAs Important difference: ISA vs. Implementation Open Instruction Set Architecture (ISA) Define the basic interface between SW and HW ISAs don t matter, ISAs do matter (K. Asanovic) Can have proprietary implementations Closed ISA: Patents on parts in the ISA 3
4 Benefits of an Open ISA Innovation and broader market Boost open source ecosystem Availability of hardware Shared tools and software ecosystem Reduced costs Real architecture research and education Closed ISAs change with their companies 4
5 Popular Open ISAs Sparc V8: 32-bit ISA by Sun (1990) Adopted as (now inactive) IEEE OpenRISC Started as a student project, first release: 2000 Active, but small community 5
6 RISC-V: The new star open ISA Started in 2010, UCB Aspire Lab Based on standard RISC principles Base standard extensions (32, 64, 128 bit) Integral design concept: custom extensions RISC-V Foundation governs the ISA Many industry members A lot of traction 6
7 Take me to the open processors! Chuck Coker via Flickr, CC BY 2.0
8 Open Source Processors Open Closed T1 Sparc V8 S1 Leon OpenRISC T2 Leon2 Leon3 Leon 4 OR1200 OR1ON mor1kx Samsung BA12 etc. ar100 J1 J2 SH lm32 Amber ARM V
9 RISC-V Processors Open Closed Sodor Sodor Sodor Rocket z-scale BOOM HWACHA SHAKTI SHAKTI SHAKTI RI5CY Open-V picorv32 riscy OPA urv NV RISC-V GRVI SCRx CORE_RISCV
10 LowRISC: An open RISC-V SoC Not-for-profit, since 2014 Linux of the Hardware World Goal: Produce entirely open SoC, high-quality, secure base for derived works Features: Tagged memory Minion cores Three releases so far, next in March Other activities: RISC-V LLVM 10
11 Free and Open Source Silicon Hardware was open in the beginning, but Dense integration into single chips It has become a critical, expensive venture Uprising of Open Source Digital Design First significant wave with opencores.org FPGAs are probably the key enabler Recently: many open source hardware projects But: Development of open source IP still in its very beginning, learn from software and makers 11
12 When I think of hardware development... Screenshot from Mentor Graphics HDL Designer v (own work)
13 How can we improve that, especially for FOSSi? Photo by VFS Digital Design via Flickr, CC-BY 2.0
14 FOSSi Foundation Non-profit organization Started from OpenRISC community Not happy with stagnation of opencores.org Goal: Advance Free and Open Source Silicon Three main activities of FOSSi Community hub LibreCores.org Licensing Community Involvement, Conference 14
15 We need more collaboration! Kevin Dooley via Flickr, CC BY What can we learn from software development and what not? 15
16 Say Hello to LibreCores!
17 LibreCores Status & Plans Heavy development, currently basic features We don t host code, others do that better Present metadata around your core Focus is on trust, collaboration, integration Plans for 2017: Quality Metrics (machine-/community-generated) API-Integration with package managers Extensive tutorials and best-practices (How to host, publish, license, etc.) 17
18 Jenkins logo: CC BY-SA 3.0 jenkins.io LibreCores Continuous Integration LibreCores CI Code Repository You FPGA board: Sparkfun CC BY-NC-SA 3.0 Simulation Nodes FPGA Agents 18
19 The inevitable topic verkeorg via Flickr, CC BY-SA 2.0
20 Licensing Area of most confusion FOSSi Foundation licensing committee Publish articles about license choices Roadmap 2017: Three recommendations Permissive license: Solderpad License Weak copyleft: GPL+?, OHDL Strong copyleft: GPL+?, CERN OHL 20
21 Community Events Upcoming: Open Silicon and RISC-V Munich, 23 March, 2017 Krste Asanovic, UC Berkeley: RISC-V Rob Mullins, Alex Bradbury, Uni Cambridge: lowrisc Me: FOSSi Foundation Highlight: Our annual conference: ORCONF Started as OpenRISC meeting in 2012 Open source digital designs and ecosystem, open source EDA Cambridge 2013 (25 people), Munich 2014 (35), Geneva 2015 (90 people), Bologna 2016 (120 people) 21
22 Isn t that a picturesque place? Rochdale Canal at Hebden Bridge. Poliphilo via Wikimedia Commons, CC0 State of Open Source Processors and Open Source Silicon 22
23 ORConf 2017 September 8 10, Hebden Bridge, UK Part of Wuthering Bytes Festival
24 let's talk! ht tps :// Find sp ea the s ke rd lides ec k.c at: om /w all en t me FOSSi Foundation Stefan Wallentowitz discussion@lists.librecores.org wallento@fossi-foundation.org #librecores on freenode You can freely remix this presentation under the terms of the Creative Commons BY-SA 4.0 license. o
Fast architecture prototyping on FPGAs: frameworks, tools, and challenges
Fast architecture prototyping on FPGAs: frameworks, tools, and challenges Philipp Wagner Technische Universität München Lehrstuhl für Integrierte Systeme 10.04.2017 Our Goal: Improving MPSoC Architectures
Bringing up cycle-accurate models of RISC-V cores.
Bringing up cycle-accurate models of RISC-V cores ed.jones@embecosm.com About me and Embecosm Work on open source tool chains at Embecosm LLVM, GNU Binutils, Newlib, Energy efficiency in compilers (TSERO)
RISC-V Updates Krste Asanović krste@berkeley.edu http://www.riscv.org 3 rd RISC-V Workshop Oracle, Redwood Shores, CA January 5, 2016 Agenda UC Berkeley updates RISC-V transition out of Berkeley Outstanding
The lowrisc project Alex Bradbury
The lowrisc project Alex Bradbury lowrisc C.I.C. 3 rd April 2017 lowrisc We are producing an open source Linux capable System-on-a- Chip (SoC) 64-bit multicore Aim to be the Linux of the Hardware world
OpenRISC Talk. Stafford Horne
OpenRISC Talk Stafford Horne What is OpenRISC? FPGA, IP cores OpenCores FuseSOC FOSSi What is OpenRISC? Officially OpenRISC 1000 is an open source RISC architecture: 32-bit / 64-bit 32 General Purpose
RISC-V. Palmer Dabbelt, SiFive COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.
RISC-V Palmer Dabbelt, SiFive Why Instruction Set Architecture matters Why can t Intel sell mobile chips? 99%+ of mobile phones/tablets are based on ARM s v7/v8 ISA Why can t ARM partners sell servers?
Two routes to specialisation: Loki and lowrisc. Robert Mullins, University of Cambridge WEEE September 2015 Espoo, Finland
Two routes to specialisation: Loki and lowrisc Robert Mullins, University of Cambridge WEEE 10-12 September 2015 Espoo, Finland Specialisation More transistors but end of Dennard scaling Dark silicon,
Industrial-Strength High-Performance RISC-V Processors for Energy-Efficient Computing
Industrial-Strength High-Performance RISC-V Processors for Energy-Efficient Computing Dave Ditzel dave@esperanto.ai President and CEO Esperanto Technologies, Inc. 7 th RISC-V Workshop November 28, 2017
Workshop on Open Source Hardware Development Tools and RISC-V
Workshop on Open Source Hardware Development Tools and RISC-V MohammadHossein AskariHemmat Shahid Bahonar University of Kerman August 24, 2017 MohammadHossein AskariHemmat Workshop on RISC-V August 24,
CS 152 Computer Architecture and Engineering Lecture 1 Single Cycle Design
CS 152 Computer Architecture and Engineering Lecture 1 Single Cycle Design 2014-1-21 John Lazzaro (not a prof - John is always OK) TA: Eric Love www-inst.eecs.berkeley.edu/~cs152/ Play: 1 Today s lecture
Introduction to RISC-V
Introduction to RISC-V Jielun Tan, James Connolly February, 2019 Overview What is RISC-V Why RISC-V ISA overview Software environment Beta testing What is RISC-V RISC-V (pronounced risk-five ) is an open,
A Perspective on the Role of Open-Source IP In Government Electronic Systems
A Perspective on the Role of Open-Source IP In Government Electronic Systems Linton G. Salmon Program Manager DARPA/MTO RISC-V Workshop November 29, 2017 Distribution Statement A (Approved for Public Release,
SOFTWARE DRIVES HARDWARE, LESSONS LEARNED AND FUTURE DIRECTIONS
SOFTWARE DRIVES HARDWARE, LESSONS LEARNED AND FUTURE DIRECTIONS Rob Oshana Vice President, Software Engineering, R&D NXP Semiconductors Microcontroller and Microprocessors PUBLIC USE Key messages Software
ECE 111 ECE 111. Advanced Digital Design. Advanced Digital Design Winter, Sujit Dey. Sujit Dey. ECE Department UC San Diego
Advanced Digital Winter, 2009 ECE Department UC San Diego dey@ece.ucsd.edu http://esdat.ucsd.edu Winter 2009 Advanced Digital Objective: of a hardware-software embedded system using advanced design methodologies
Technical Committee Update
Technical Committee Update Yunsup Lee and Silviu Chiricescu yunsup@sifive.com silviu.chiricescu@baesystems.com RISC-V Foundation 1 Technical Committee Goals Maintain a roadmap of the RISC-V ISA Coordinate
RISC V - Architecture and Interfaces
RISC V - Architecture and Interfaces The RocketChip Moritz Nöltner-Augustin Institut für Technische Informatik Lehrstuhl für Rechnerarchitektur Universität Heidelberg February 6, 2017 Table of Contents
So you think developing an SoC needs to be complex or expensive? Think again
So you think developing an SoC needs to be complex or expensive? Think again Phil Burr Senior product marketing manager CPU Group NMI - Silicon to Systems: Easy Access ASIC 23 November 2016 Innovation
Author(s): August E. Evrard, PhD. 2010
Author(s): August E. Evrard, PhD. 2010 License: Unless otherwise noted, this material is made available under the terms of the Creative Commons Attribution-Non-commercial-Share Alike 3.0 License: http://creativecommons.org/licenses/by-nc-sa/3.0/
Custom Silicon for all
Custom Silicon for all Because Moore s Law only ends once Who is SiFive? Best-in-class team with technology depth and breadth Founders & Execs Key Leaders & Team Yunsup Lee CTO Krste Asanovic Chief Architect
The Semantic Web DEFINITIONS & APPLICATIONS
The Semantic Web DEFINITIONS & APPLICATIONS Data on the Web There are more an more data on the Web Government data, health related data, general knowledge, company information, flight information, restaurants,
Outline. Debug Working Group Intro Why does RISC-V need an External Debug Spec? Overview of the Debug Spec v. 013 Future tasks of Debug Working Group
Outline Debug Working Group Intro Why does RISC-V need an External Debug Spec? Overview of the Debug Spec v. 013 Future tasks of Debug Working Group 2 Debug Working Group Intro History of the current Specification
2. HW/SW Co-design. Young W. Lim Thr. Young W. Lim 2. HW/SW Co-design Thr 1 / 21
2. HW/SW Co-design Young W. Lim 2016-03-11 Thr Young W. Lim 2. HW/SW Co-design 2016-03-11 Thr 1 / 21 Outline 1 Software Engineering Young W. Lim 2. HW/SW Co-design 2016-03-11 Thr 2 / 21 Based on Software
Anonymity, Usability, and Humans. Pick Two.
Anonymity, Usability, and Humans. Pick Two. Runa A. Sandvik runa@torproject.org 20 September 2011 Runa A. Sandvik runa@torproject.org () Anonymity, Usability, and Humans. Pick Two. 20 September 2011 1
Improving the Performance Per Area Factor of RISC-V Based Multi-Core Systems
Improving the Performance Per Area Factor of RISC-V Based Multi-Core Systems Tobias Strauch R&D, EDAptix, Munich, Germany tobias@edaptix.com 4th RISC-V Workshop at MIT, Boston, USA July 13, 2016 Agenda
BUSINESS 478. Section D400 CASE SYNOPSIS FOR: SAMSUNG
BUSINESS 478 Section D400 CASE SYNOPSIS FOR: SAMSUNG Matthew Cheah Yu Liu Jacky Pan Louisa Qiu Date: March 21, 2013 INTRODUCTION History In 1938, Samsung was founded by Byung-Chull Lee as a small export
Hardware-Software Co-Design and Prototyping on SoC FPGAs Puneet Kumar Prateek Sikka Application Engineering Team
Hardware-Software Co-Design and Prototyping on SoC FPGAs Puneet Kumar Prateek Sikka Application Engineering Team 2015 The MathWorks, Inc. 1 Agenda Integrated Hardware / Software Top down Workflow for SoC
Resource upload / download guide
The Higher Education Academy / JISC Open Educational Resources Programme Resource upload / download guide Authors: Liam Comerford, John Connor Date: 12/04/2010 Version: 2 This guide helps talk you through
Roadmap Directions for the RISC-V Architecture
Roadmap Directions for the RISC-V Architecture Andes RISC-V Con November 13, 2018 Linley Gwennap, Principal Analyst About Linley Gwennap Founder, principal analyst, The Linley Group Leading vendor of technical
University co-operation with Maemo SW FRUCT seminar Tampere Nokia V1-Filename.ppt / YYYY-MM-DD / Initials
University co-operation with Maemo SW FRUCT seminar Tampere 29.10.2008 1 2008 Nokia V1-Filename.ppt / YYYY-MM-DD / Initials Contents Maemo SW The upcoming Maemo 5 (Fremantle) release The meamo open source
Chisel to Chisel 3.0.0
Chisel 2.0.0 to Chisel 3.0.0 Generators: Type-Safe Meta-Programming for RTL Design Reuse Type-Safety Powerful Language Features 4 Hired Jonathan Bachrach 5 At the end of ParLab, we solved hardware design
An NVMe-based Offload Engine for Storage Acceleration Sean Gibb, Eideticom Stephen Bates, Raithlin
An NVMe-based Offload Engine for Storage Acceleration Sean Gibb, Eideticom Stephen Bates, Raithlin 1 Overview Acceleration for Storage NVMe for Acceleration How are we using (abusing ;-)) NVMe to support
NPLN the answer to EDA, the repair universe and everything FOSDEM' Brussels / 30 & 31 January 2016
FOSDEM' 16 Brussels / 30 & 31 January 2016 Hagen Sankowski PGP Key: 4096R/CA00D412 hsank@nospam.chipforge.org Intro '' still does not has a deeper meaning 1st code name was 'Napoleon' short, w/o all vowels
Easy Multicore Programming using MAPS
Easy Multicore Programming using MAPS Jeronimo Castrillon, Maximilian Odendahl Multicore Challenge Conference 2012 September 24 th, 2012 Institute for Communication Technologies and Embedded Systems Outline
A Big Little Hypervisor for IoT Development February 2018
A Big Little Hypervisor for IoT Development February 2018 Contents PROJECT OVERVIEW TECHNICAL OVERVIEW GOVERNANCE JOIN US! PROJECT OVERVIEW Current State of Affairs IoT Development IoT device devices requires
E-Commerce Systems. Outline of the Talk. Who am I? (continued) Who am I? 2016/2/19. Spring 2016, Room #E74 Tuesday 1:20pm 4:10pm
Spring 2016, Room #E74 Tuesday 1:20pm 4:10pm Course Overview and Introduction Outline of the Talk Introduction to Dr. Chien-Hua Tsai( 蔡建華 ) Goals of the course Course requirements Administrative details
Build the unified end to end IoT solution on ARM LEADING COLLABORATION IN THE ARM ECOSYSTEM
Build the unified end to end IoT solution on ARM LEADING COLLABORATION IN THE ARM ECOSYSTEM Agenda Linaro Linaro s IoT efforts Demo Business Models Design and sell x86 chips 2016 $59.5Bn Revenue Sells
Hardware Level Organization
Hardware Level Organization Intro MIPS 1 Major components: - memory - central processing unit - registers - the fetch/execute cycle CPU PC IR Ex Unit MAR MBR I/O AR I/O BR System Bus Main Memory 0 (the
A Retrospective on Par Lab Architecture Research
A Retrospective on Par Lab Architecture Research Par Lab SIGARCH Krste Asanovic, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, Sarah Bird, Alex Bishara, Chris Celio, Henry Cook, Ben Keller, Yunsup
Welcome to Islandora Camp UK. London, May 7-9, 2014
Welcome to Islandora Camp UK London, May 7-9, 2014 Our Day Who are we? Logistics: Wireless (11-12 session) Schedule for the camp available here: http://islandora. ca/camps/uk2014/schedule Overview of the
: Course : SharePoint 2016 Site Collection and Site Administration
Module Title Duration : Course 55194 : SharePoint 2016 Site Collection and Site Administration : 5 days Course Description This five-day instructor-led course is intended for power users and IT professionals,
Copyright CAUSE This paper was presented at the 1993 CAUSE Annual Conference held in San Diego, California, December 7-10, and is part of the
Copyright CAUSE 1994. This paper was presented at the 1993 CAUSE Annual Conference held in San Diego, California, December 7-10, and is part of the conference proceedings published by CAUSE. Permission
Embedded Systems: Projects
November 2016 Embedded Systems: Projects Davide Zoni PhD email: davide.zoni@polimi.it webpage: home.dei.polimi.it/zoni Contacts & Places Prof. William Fornaciari (Professor in charge) email: william.fornaciari@polimi.it
Introduction. Overview of the Book
Introduction This book is for developers. It will get you up and running with your first bada app, quickly. Looking beyond your first app, we hope this book will find a permanent place on your desk as
Replicant Keynote. Paul Kocialkowski Saturday June 4 th 2016
Replicant Keynote Paul Kocialkowski paulk@replicant.us Saturday June 4 th 2016 Components, Issues and Freedom Components and Implementations Components of a mobile device: Processors Primary processor
CLICK TO EDIT MASTER TITLE STYLE. Click to edit Master text styles. Second level Third level Fourth level Fifth level
CLICK TO EDIT MASTER TITLE STYLE Second level THE HETEROGENEOUS SYSTEM ARCHITECTURE ITS (NOT) ALL ABOUT THE GPU PAUL BLINZER, FELLOW, HSA SYSTEM SOFTWARE, AMD SYSTEM ARCHITECTURE WORKGROUP CHAIR, HSA FOUNDATION
Igniting the Open Hardware Ecosystem with RISC-V
Igniting the Open Hardware Ecosystem with RISC-V FOSDEM, February 2018 Palmer Dabbelt, SiFive Yunsup Lee, SiFive RISC-V is a free and open ISA standard designed for all computing devices RISC-V binutils,
Let's Treat the Eclipse IDE More Like a Product. Productizing open source Eclipse IDEs
Let's Treat the Eclipse IDE More Like a Product Productizing open source Eclipse IDEs What is a Product? a thing produced by labor a person or thing produced by or resulting from a process an article or
ECE 468 Computer Architecture and Organization Lecture 1
ECE 468 Computer Architecture and Organization Lecture 1 September 7, 1999 ece 468 Intro.1 What is "Computer Architecture" Co-ordination of levels of abstraction Application Compiler Instr. Set Proc. Operating
Evaluating RISC-V Cores for PULP
Evaluating RISC-V Cores for PULP An Open Parallel Ultra-Low-Power Platform www.pulp.ethz.ch 30 June 2015 Sven Stucki Antonio Pullini Michael Gautschi Frank K. Gürkaynak Andrea Marongiu Igor Loi Davide
When Will SystemC Replace gcc/g++? Bodo Parady, CTO Pentum Group Inc. Sunnyvale, CA
When Will SystemC Replace gcc/g++? Bodo Parady, CTO Pentum Group Inc. Sunnyvale, CA 94087 bparady@pentum.com SystemC: The Next Programming Who Language Who will support future system development? What
Innovation in System Design Enablement. Cadence Design Systems, Inc. Graser Technology Conference October 2015
Innovation in System Design Enablement Cadence Design Systems, Inc. Graser Technology Conference October 2015 Social trends driving multiple layers of technology Datacenter Office Cloud Gateway Device
The Future of Security is in Open Silicon Linux Security Summit 2018
The Future of Security is in Open Silicon Linux Security Summit 2018 Joel Wittenauer - Embedded Software Architect Rambus Cryptography Research August 28, 2018 Agenda About Rambus Cryptography Research
ODPi and Data Governance Free Your MetaData! October 10, 2018
ODPi and Data Governance Free Your MetaData! October 10, 2018 Today s reality @ODPiOrg Imagine An enterprise data catalogue that lists all of your data, where it is located, its origin (lineage), owner,
A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators"
A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W ISC-V Processor with Vector Accelerators" Yunsup Lee 1, Andrew Waterman 1, imas Avizienis 1,! Henry Cook 1, Chen Sun 1,2,! Vladimir Stojanovic 1,2, Krste Asanovic
Preparing for Jenkins Certification
Preparing for Jenkins Certification Agenda Jenkins Certification Prerequisites What exam do you plan to take? How to schedule and register for the test? Structure of the exams Plugins Organization of the
SDN and NFV as expressions of a systemic trend «integrating» Cloud, Networks and Terminals
SDN and NFV as expressions of a systemic trend «integrating» Cloud, Networks and Terminals Antonio Manzalini, Chair of the IEEE SDN initiative Bobby Wong, Program Director SDN-NFV Standardization Committee
Evaluation of RISC-V RTL with FPGA-Accelerated Simulation
Evaluation of RISC-V RTL with FPGA-Accelerated Simulation Donggyu Kim, Christopher Celio, David Biancolin, Jonathan Bachrach, Krste Asanovic CARRV 2017 10/14/2017 Evaluation Methodologies For Computer
Best Practices and Lessons Learned using GitHub for Corporate Open Source Charles Eckel / Cisco DevNet
Best Practices and Lessons Learned using GitHub for Corporate Open Source Charles Eckel / Cisco DevNet @eckelcu Agenda Goal and reality GitHub guidance Orgs Membership and permissions Contributions Licensing
"Charting the Course... MOC A: SharePoint 2016 Site Collections and Site Owner Administration. Course Summary
MOC 55234 A: 2016 Site Collections Course Summary Description This five-day instructor-led course is intended for power users and IT professionals who are tasked with working within the 2016 environment
Training & Certification Guide
Training & Certification Guide Pragmatic EA Ltd December 2010 Version 2.0.5 Part of the Pragmatic Family Cutting Architecture To the Bone Contents INTRODUCTION 3 What is PEAF 3 Aim of this document 3 Non-Commercial
Tool Repositories, ESCHER and continuing the legacy of the CHESS ITR
Tool Repositories, ESCHER and continuing the legacy of the CHESS ITR Edited and Presented by Janos Sztipanovits ISIS, Vanderbilt University Chess Review October 4, 2006 Alexandria, VA ESCHER Research Institute
ECE 471 Embedded Systems Lecture 2
ECE 471 Embedded Systems Lecture 2 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 7 September 2018 Announcements Reminder: The class notes are posted to the website. HW#1 will
Hardware Acceleration for Tagging
Parallel Hardware Parallel Applications IT industry (Silicon Valley) Parallel Software Users Hardware Acceleration for Tagging Sarah Bird, David McGrogan, John Kubiatowicz, Krste Asanovic June 5, 2008
CADENCE DESIGN SYSTEMS, INC. Second Quarter 2018 Financial Results Conference Call
Page 1 CADENCE DESIGN SYSTEMS, INC. Second Quarter 2018 Financial Results Conference Call Prepared Remarks of Lip-Bu Tan, Chief Executive Officer and John Wall, Senior Vice President and Chief Financial
Embedded Hardware and Software
Embedded Hardware and Software Saved by a Common Language? Nithya A. Ruff, Director, Product Marketing 10/11/2012, Toronto Synopsys 2012 1 Synopsys Industry Leadership $1,800 $1,600 $1,400 $1,200 $1,000
Expanding Opportunities in Clamshell Devices. Laurence Bryant VP Strategic Marketing
Expanding Opportunities in Clamshell Devices Laurence Bryant VP Strategic Marketing 1 PC Mobile Ecosystem Scaling The Richness Of Small Screen Experiences The smartphone and tablet ecosystem is shaping
Lesson 10 Thinking about Structure
Lesson 10 Thinking about Structure Objectives In this tutorial we will: Explain the parent - child relationship for creating structured content; introducing templates as a mechanism for navigation; and
Strober: Fast and Accurate Sample-Based Energy Simulation Framework for Arbitrary RTL
Strober: Fast and Accurate Sample-Based Energy Simulation Framework for Arbitrary RTL Donggyu Kim, Adam Izraelevitz, Christopher Celio, Hokeun Kim, Brian Zimmer, Yunsup Lee, Jonathan Bachrach, Krste Asanović
Jisc Research Data Shared Service. Looking at the past, looking to the future
Jisc Research Data Shared Service Looking at the past, looking to the future A retrospective Sometimes in order to keep moving forward, not only must you take one step at a time, but you must be willing
MS PowerPoint Intermediate
Lesson Plan Rev. 11/16 MS PowerPoint Intermediate I. Introduction Introductions Housekeeping o Location of restrooms o Length of class o Encourage questions during class o Assure students they can sit
OUTLINE OF THIS PRESENTATION
CREATING, ACQUIRING AND INTEGRATING REUSABLE IP Prof. Don Bouldin, Ph.D. Electrical & Computer Engineering University of Tennessee Knoxville, TN 37996-2100 dbouldin@tennessee.edu IEEE Boston 14 November
CREATING, ACQUIRING AND INTEGRATING REUSABLE IP
CREATING, ACQUIRING AND INTEGRATING REUSABLE IP Prof. Don Bouldin, Ph.D. Electrical & Computer Engineering University of Tennessee Knoxville, TN 37996-2100 dbouldin@tennessee.edu IEEE Boston 14 November
hidglobal.com HID ActivOne USER FRIENDLY STRONG AUTHENTICATION
HID ActivOne USER FRIENDLY STRONG AUTHENTICATION We understand IT security is one of the TOUGHEST business challenges today. HID Global is your trusted partner in the fight against data breach due to misused
55033: SHAREPOINT 2013 SITE COLLECTION AND SITE ADMINISTRATION
ABOUT THIS COURSE This five-day instructor-led course is intended for power users, who are tasked with working within the SharePoint 2013 environment. This course will provide a deeper, narrowly-focused
SharePoint 2013 Site Collection and Site Administration
SharePoint 2013 Site Collection and Site Administration Course 55033; 5 Days, Instructor-led Course Description This five-day instructor-led course is intended for power users, who are tasked with working
Website Designs Australia
Proudly Brought To You By: Website Designs Australia Contents Disclaimer... 4 Why Your Local Business Needs Google Plus... 5 1 How Google Plus Can Improve Your Search Engine Rankings... 6 1. Google Search
Alcatel-Lucent invents and delivers the innovative networks of tomorrow.
Alcatel-Lucent invents and delivers the innovative networks of tomorrow. Every success has its network. Alcatel-Lucent is the leading IP networking, ultra-broadband access, and cloud technology specialist.
A New Era of Silicon Prototyping in Computer Architecture Research
A New Era of Silicon Prototyping in Computer Architecture Research Christopher Torng Computer Systems Laboratory School of Electrical and Computer Engineering Cornell University Recent History of Prototypes
Revolutionizing Open. Cecilia Carniel IBM Power Systems Scale Out sales
Revolutionizing Open Cecilia Carniel IBM Power Systems Scale Out sales cecilia_carniel@it.ibm.com Copyright IBM Corporation 2015 Technical University/Symposia materials may not be reproduced in whole or
Introducing K-12 Solutions for:
Introducing K-12 Solutions for: Mobile Devices Collaboration Software Mobile Peripherals Content Filtering Mobile Device Management (MDM) Curriculum Configuration Services Wireless Infrastructure Learning
Targeting Motor Control Algorithms to System-on-Chip Devices
Targeting Motor Control Algorithms to System-on-Chip Devices Dr.-Ing. Werner Bachhuber 2015 The MathWorks, Inc. 1 Why use Model-Based Design to develop motor control applications on SoCs? Enables early
TUTORIAL - HOW TO ACCESS YOUR SESSIONS
TUTORIAL - HOW TO ACCESS YOUR SESSIONS Visit: www.rims.org/ssc You will be prompted to login with your email address and RIMS password. If you don t know your password kindly contact Kamy, kpersaud@rims.org
Hardware accelerated approach for floating-point multiplication on 32-bit pipelined RISC-V processor
Hardware accelerated approach for floating-point multiplication on 32-bit pipelined RISC-V processor 271 IJCTA, 9(23), 2016, pp. 271-276 International Science Press Hardware accelerated approach for floating-point
An Incubator Project in the Apache Software Foundation. 13 July 2016
An Incubator Project in the Apache Software Foundation http://mynewt.apache.org/ 13 July 2016 Apache Mynewt Open Source OS for Constrained IoT MCU / Hardware independent ARM Cortex-M*, AVR, MIPS, more...
Giving Everyone Access To Open Source Best Prac8ces
Giving Everyone Access To Open Source Best Prac8ces OpenChain Project - The Linux Founda8on Available under the CC ACribu8on-NoDeriva8ves 4.0 Interna8onal license. The value of open source is efficiency:
Introducing Hellenic Conference of Academic Libraries
Introducing SciVerse @19th Hellenic Conference of Academic Libraries Eduardo Ramos Account Development Manager Southern Europe & Israel e.ramossilva@elsevier.com Table of Contents 1. Why is Elsevier Launching
Adventures in Drupalia
Adventures in Drupalia Drupal from an outsider s perspective Paul Nijjar Kitchener-Waterloo Linux User Group Toronto DrupalCamp 2012 November 17-18, 2012 What is Drupal? Drupal is... A content management
RISC-V Summit, December 2018 Simon Davidmann, Lee Moore 2018, Imperas Software
How to Address RISC-V Compliance in the Era of OPEN ISA and Custom Instructions RISC-V Summit, December 2018 Simon Davidmann, Lee Moore 2018, Imperas Software Agenda RISC-V Compliance Compliance for RISC-V
Cyberinfrastructure Component: Goals, Strategies, Progress and Plans
Nevada NSF EPSCoR Climate Change Conference Cyberinfrastructure Component: Goals, Strategies, Progress and Plans Sergiu Dascalu February 2, 2010 Overview Team Goal and Targets Strategies and Activities
Samsung Welcomes OCP s ODSA. Craig Orr Sr. Director of D/C, AI, Networking segments, Samsung Foundry March 28, 2019
Samsung Welcomes OCP s ODSA Craig Orr Sr. Director of D/C, AI, Networking segments, Samsung Foundry March 28, 2019 Topics 1. You are here (where DSA fits within Samsung) 2. FYI on Samsung foundry (expansion
Arm Processor Technology Update and Roadmap
Arm Processor Technology Update and Roadmap ARM Processor Technology Update and Roadmap Cavium: Giri Chukkapalli is a Distinguished Engineer in the Data Center Group (DCG) Introduction to ARM Architecture
Untethered lowrisc, Memory Mapped IO and TileLink/AXI. Wei Song 27/07/2015
Untethered lowrisc, Memory Mapped IO and /AXI Wei Song 27/07/2015 Time Line expected Nov. 2014 Apr. 2015 Now Oct. 2015 -Chip release from Berkeley First lowrisc release. Memeory Mapped IO. Untethered lowrisc
CHURCHILL FELLOWS COMMUNITY FORUM Powered by
Welcome to the new CHURCHILL FELLOWS COMMUNITY FORUM Powered by Discourse is a Simple. Modern. Fun. user friendly discussion platform! We recommend exploring it by clicking into different areas to find
OWASP - SAMM. OWASP 12 March The OWASP Foundation Matt Bartoldus Gotham Digital Science
OWASP - SAMM Matt Bartoldus Gotham Digital Science OWASP 12 March 2009 Copyright The OWASP Foundation Permission is granted to copy, distribute and/or modify this document under the terms of the OWASP
Balloon Open Hardware Licence
(Balloonz / Toby Churchill Ltd) wookey@wookware.org FOSDEM 2007, Brussels 1 2 What is? Documented Interface/hardware Free firmware VHDL (CPUs, subsystems) - OpenCores.org Open designs RepRap machine What
The Penguin and the Droid
The Penguin and the Droid Robert Berger Reliable Embedded Systems 2012 by Robert Berger - Reliable Embedded Systems cbna CC-Licence: http://creativecommons.org/licenses/by-nc-sa/3.0/ last commit: 2012-03-10
SiFive Freedom SoCs: Industry s First Open-Source RISC-V Chips
SiFive Freedom SoCs: Industry s First Open-Source RISC-V Chips Yunsup Lee Co-Founder and CTO High Upfront Cost Has Killed Innovation Our industry needs a fundamental change Total SoC Development Cost Design
Basic Campus Design Concepts
Basic Campus Design Concepts Campus Network Design & Operations Workshop These materials are licensed under the Creative Commons Attribution-NonCommercial 4.0 International license (http://creativecommons.org/licenses/by-nc/4.0/)
ECE 486/586. Computer Architecture. Lecture # 7
ECE 486/586 Computer Architecture Lecture # 7 Spring 2015 Portland State University Lecture Topics Instruction Set Principles Instruction Encoding Role of Compilers The MIPS Architecture Reference: Appendix
mygateway Portal Training for Staff
mygateway Portal Training for Staff Index What Is A Portal?... 4 Portal Terms... 4 Signing In To Mygateway... 5 Terms in Use... 6 Channels... 7 Remove / Add a Channel... 7 Content Layout... 8 Order of