Untethered lowrisc, Memory Mapped IO and TileLink/AXI. Wei Song 27/07/2015

Transcription

1 Untethered lowrisc, Memory Mapped IO and /AXI Wei Song 27/07/2015

2 Time Line expected Nov Apr Now Oct Chip release from Berkeley First lowrisc release. Memeory Mapped IO. Untethered lowrisc release. Initial tagged memory support. Added tags in L1 D$, L2. Added a tag cache. Added 2 instructions to load/ store tag. A tutorial about -chip. Untethered SoC. Support Kintex KC705. Support MMIO. Support SD, UART, DDRAM. Open simulation environment. 2

3 -Chip Release (Berkeley) Tile Tile Tile Host Interface ARM UART SD EtherNet MemIO Converter Memory Controller 3

4 lowrisc Release (tagged memory) Tile Tile Tile Host Interface ARM UART SD EtherNet Tag Cache Allocator Tag in L1 D$, L2 $ Tag Cache LTAG/STAG instructions Data Array MetaData Array Tracker & Converter Memory Controller 4

5 Latest -Chip (Berkeley) Tile Tile Tile Host Interface ARM UART SD L2 Bus EtherNet Cached Uncached AXI MemIO AXI Bus Memory Controller /AXI AXI/MemIO Multi-beat Standardize transactions Possible coherence support of L3 Code refactoring AXI/AXI interface (NASTI) 5

6 Untethered lowrisc SoC (First Version) Tile Tile Tile Cached Uncached AXI AXI-Lite L2 Cache Bus L2 IO Bus DMA coherent Boot Minion /AXI-Lite Tag Cache UART SD EtherNet DMA AXI Bus /AXI incoherent On-FPGA Boot Ram Memory Controller 6

7 Current Status Tile Tile Tile Cached Uncached AXI AXI-Lite L2 Cache Bus L2 IO Bus DMA coherent Boot Minion /AXI-Lite Tag Cache UART SD EtherNet DMA AXI Bus /AXI incoherent On-FPGA Boot Ram Memory Controller 7

8 Memory Mapped IO Target IO load/write (B/HW/W/DW) In-order uncached load/store Side effect None for all write in units of byte None for all read in units of word (32-bit AXI-Lite) No change in current L2 coherent manager 8

9 Untethered lowrisc SoC (First Version) Tile Tile Tile Cached Uncached AXI AXI-Lite L2 Cache Bus L2 IO Bus DMA coherent Boot Minion /AXI-Lite Tag Cache UART SD EtherNet DMA AXI Bus /AXI AXI/AXI-Lite incoherent On-FPGA Boot Ram Memory Controller 9

10 L1 Data Cache mem.finish mem.req mem.grant mem.probe cpu.ptw cpu.req wb.meta/data_read prober.meta/data_read mshrs.replay s1_recycled mshrs [MSHRFile;rocket/nbdcache.scala] mshr [MSHR rocket/nbdcache.scala] dtlb.ptw meta [MetadataArray uncore/cache.scala] read data [DataArray rocket/nbdcache.scala] read resp resp s1_req mshrs.meta_write mshrs.request s2_recycle = s1_req.addr = dtlb [TLB rocket/tlb.scala] = = s1_tag_eq_way s1_data vpn ppn s2_req s1_addr Stage 1 Stage 2 mshrs.wb_req s2_tag_eq_way s2_data prober [ProbeUnit;rocket/nbdcache.scala] req wb_req meta/data read rep meta_write line_state s2_data_correctable s2_data (uncorrected) amoalu [AMOALU rocket/nbdcache.scala] rhs lhs cpu.resp.bits.data s2_hit s2_hit code [DecodeLogic rocket/decode.scala] correctable prober.meta_write out in out correct s3_req s2_data (corrected) cpu.resp.valid 0 1 Arb wb [WriteBack;rocket/nbdcache.scala] Arb Arb meta/data read req prober.release Stage 3 Stage 4 s2_data (corrected) 1 write data_resp release 0 1 meta [MetadataArray uncore/cache.scala] write Arb data [DataArray rocket/nbdcache.scala] mem.release 10

11 L1 Data Cache (simplified) mem.req mem.grant mshrs mshr mshrs.replay mshrs.meta_write mshrs.request s2_hit meta s1_req s1_req.addr vpn dtlb ppn s1_addr s2_req s2_hit meta cpu.req read data read resp resp = s1_addr = = = s1_tag_eq_way s2_data s1_data amoalu rhs out lhs Arb write write data Stage 1 Stage 2 Stage 3 Stage 4 cpu.resp 11

12 L1 Data Cache with IO Handler mem.req mem.grant io.req io.grant mshrs mshr mshrs.replay mshrs.meta_write mshrs.request iomshr.replay io_data s1_io_data replay io_data request iomshr cpu.req meta read data read s1_req s1_req.addr vpn dtlb ppn s1_addr resp s1_addr = = = = s1_tag_eq_way s2_data resp s1_data s2_req s2_io_replay s2_hit s2_io_data ioaddr addr io s2_req.addr amoalu rhs out lhs Arb write write meta data Stage 1 Stage 2 Stage 3 Stage 4 cpu.resp 12

13 Channels /Client : Coherent manager or next level cache/device Client: upper level cache 5 Channels Acquire: [C -> M] Read, uncached write (write-through, IO), permission update Grant: [M -> C] Ack to Acquire (with data when read) Finish: [C -> M] Finish a transaction Probe: [M -> C] probe (snoop, invalidate) Release: [C -> M] Write-back (replace or invalidate) 13

14 Untethered lowrisc SoC (First Version) Tile Tile Tile Cached Uncached AXI AXI-Lite L2 Cache Bus L2 IO Bus DMA coherent Boot Minion /AXI-Lite Tag Cache UART SD EtherNet DMA AXI Bus /AXI AXI/AXI-Lite incoherent On-FPGA Boot Ram Memory Controller 14

15 Corssbar client Corssbar L1 $ Acquire Grant Finish Probe Release Acquire Grant Finish Probe Release L2 Bank L1 $ Acquire Grant Finish Probe Release Acquire Grant Finish Probe Release L2 Bank 15

16 Shared Corssbar client Shared Corssbar L1 $ Acquire Grant Finish Probe Release Acquire Grant Finish Probe Release L2 Bank L1 $ Acquire Grant Finish Probe Release Acquire Grant Finish Probe Release L2 Bank Use a SuperChannel to store all types of channels. 16

17 Current Status of /AXI /AXI (Berkeley, -chip) only a whole cache line /AXI-Lite (lowrisc) 1,2,4,8 byte write; 4,8 byte read AHB/APB (Berkeley, Z-Scale) Still needed: AXI/AXI-Lite compatible, auto width SerDes switch The AXI-Node from PULP May be in Chisel for its parameterization capability AXI/Wishbone, /Wishbone 17

18 Remain Issues Interrupt controller Open Sourced, License compatible IPs UART (Flexpret, BSD) SD host controller Ethernet controller (Xilinx IP for now) Memory controller (difficult to get) Open Source EDA tools Current environment: VCS (DRAMSim, Front-end server, DirectC) Vivado+SDK (SDK not available for Kintex) Target environment: Verilator (SystemVerilog 2009, SystemC, VPI, DPI) Vivado only 18

19 After the Untethered SoC Implementing the hierarchical tag cache (hardware) Debug interface Integrating minions (PULP) Tag support in cores (Lucas) 19