OpenRISC Talk. Stafford Horne
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1 OpenRISC Talk Stafford Horne
2 What is OpenRISC? FPGA, IP cores OpenCores FuseSOC FOSSi
3 What is OpenRISC? Officially OpenRISC 1000 is an open source RISC architecture: 32-bit / 64-bit 32 General Purpose Registers Delay Slot Instruction & Data MMU Linux support since mhz, 5 secs Read More:
4 OpenRISC implementations No 64-bit implementations OR original (~2000) mor1kx recommended (~2012) Modular Cappuccino - 5 stage, caching + mmu Espresso - 2 stage, no caching Pronto Espresso - 3 stage no delay slot, no caching
5 OpenRISC modular
6 OpenRISC assembly
7 OpenRISC & wishbone bus OpenRISC / opencores Standard SOC interconnect Supports common topologies Master - Slave Shared bus (multiple master) Crossbar Different pipeline burst options Read More:
8 OpenRISC vs Other soft codes Open MMU OpenRISC RISC-V LInux Upstream 32-bit Kinda 64-bit Nios2 32-bit Microblaze 32-bit Silicon Limited Soon Multi
9 FuseSOC Software world GCC, make Classpath, LD_LIBRARY_PATH import, include Hardware world SDRam Ctrl core USB core CPU core Audio core FuseSOC Vendor proprietary Xilinx/Altera Bitstream
10 A brief history OpenRISC opencores.org OpenRISC founders create Beyond Semi opencores.org changes hands ORSoC AB FOSSi create fossi-foundation.org - librecores.org freecores.github.io openrisc.io
11 FOSSi Help support and promote free and open source silicon Frontend Design - ip, simulation, analysis Backend Design - cell libraries Fabrication - cheaper processes Licencing Conferences - orconf
12 Getting Started
13 2015 I got back into fpga with a simple sound project. Designed some simple analog circuits and tied them together with a De0 Nano. Microphone Pre Amp LM741 opamp To Speaker MCP4922 DAC
14 Project Developed all by hand Spent many hours with an ISSI datasheet to learn how to write the sdram controller
15 Project - next steps After that I wanted to do more but Shareable IP Better development lifecycle (not locked into quartus) Run linux on the de0 nano
16 Toolchain GCC or1k-gcc released (needed to build or1k-linux-musl toolchain) in git and testing Upstream status - Pending in development (2016 Apr) latest 6 release (2016 Aug) latest 5 release (2016 Jun)
17 Toolchain Newlib (libc) newlib (Mar 2016) (in github) Upstream Status (~20 patches pending) (Mar 2016)
18 Toolchain Binutils/GDB Release 7.11 (upstream at 7.12) 2016 Work Testing Effort (Dejagnu) Native Simulator Support (cgen) Upstream status (patches sent) Working on fixups right now Remove doxygen Code style ChangeLog merge (since 2008) Implement pseudo registers
19 Toolchain Binutils/GDB - testing $ export DEJAGNU=../../or1k-src/boards/or1k-elf-sim.exp $ make check # # # # # # # of of of of of of of expected passes unexpected failures expected failures known failures unresolved testcases untested testcases unsupported tests (450)
20 Toolchain Binutils/GDB - sim struct data { char * str; }; struct data gdata = {.str = "global" }; char * foo(struct data tdata) { return tdata.str; } int main() { struct data tdata; tdata.str = "hello"; foo(tdata); return 0; } $ or1k-elf-gcc -g -o test test.c $ or1k-elf-gdb test (gdb) target sim (gdb) load (gdb) break main (gdb) run (gdb) print foo(gdata) $1 = 0x3bd0 global
21 Toolchain Binutils/GDB - dummy call Supporting OpenRISC abi: Structs and unions be passed as pointers Variadic arguments are passed on the stack
22 Linux No upstream patches since Feb 2012 My work so far memcpy - decrease boot time from 7 to 5 seconds bootmem to memblock conversion Upstream effort Prioritized and submitted patches for review Maintaining commit queue Patches in linux-next Stafan for Me got pgp key signature Memcpy Routine Cycs Word Copies + Loop Unrolls + Non Aligned 1882 Word Copies + Loop Unrolls 1887 Word Copies 2441 Byte Copies + Loop Unrolls 6467 Byte Copies 7600
23 Project Use openrisc soc with wishbone bus Reuse as much as possible re-write interface modules to work with wishbone bus Run Linux DMA sound card driver Controllable via UART
24 On the web github.com/openrisc - projects hosted here #openrisc on freenode (I m shorne) openrisc@lists.librecores.org openrisc.io - work in progress, moving from (opencores.org) Downloads Tutorials freecores.github.io - Opencores svn cores moved to github
25 Questions?
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