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1 Radiation Platzhalter für Characterization Bild, Bild auf Titelfolie hinter of das DDR3 Logo einsetzen SDRAM and MRAM devices - in the frame of Contract "Technology Assessment of DRAM and Advanced Memory Products" - M. Herrmann, K. Gruermann, T. Fichna, H. Michalik, IDA TU Braunschweig
2 Outline Activity background Tests Tested devices Facilities and equipment Procedures and results MRAM heavy-ion SEE DDR3 SDRAM heavy-ion SEE DDR3 SDRAM in-situ TID Conclusions FP Days ESTEC , Michalik Slide 2
3 Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Background
4 Technology Assessment of DRAM and Advanced Memory Products Contract th December 2017
5 Introduction GOAL: Characterize of the radiation hardness and the reliability of both, state of the art DRAM and advanced non-volatile memories in view of space applications. Collaboration: Airbus Defense and Space (ADS), Elancourt (ELC) / Friedrichshafen (FHN) Thales Communications & Services (T3S), Toulouse Institut für Datentechnik und Kommunikationsnetze (IDA), Braunschweig Airbus Defense and Space (ADS), Bremen Airbus Group Innovation (AGI) Comments: Two Groups of activities: Group A covering assessment of DRAM Group A activities linked to ESA study T QC Radiation Hard Memory: Radiation Testing of Candidate Memory Devices for Laplace Mission (RHM) Group B covering assessment of NVM Group B activities rearranged during the study 5
6 Work Package Description Group A WP 1000: Product and reliability assessment of commercial DRAM parts WP1100: State of the art DRAM processes (ADS & AGI) WP1200: Reliability benchmarking (ADS & AGI) WP1300: Review of any DRAM radiation test results (ADS) WP1400: DRAM device selection (ADS) WP1500: RISK analysis (ADS) WP 2000: Electrical and Radiation Characterization of the DRAM Device Type WP2100: Handling, Storage, Procurement Requirement (ADS) WP2200: Electrical Characterization (T3S) WP2300: Radiation Characterization (IDA) Heavy Ion SEE Test TID Test WP 3000: Electrical and Radiation Characterization of the DRAM Device Type WP3100: DRAM ETP Definition (ADS) WP3200: DRAM ETP Execution (T3S) 6
7 Work Package Description Group B WP 4000: Product and reliability assessment of commercial DRAM parts WP4100: State of the art NVM process technologies (IDA) WP4200: Reliability benchmarking (ADS) WP4300: Review of any NVM radiation test results (IDA & ADS) WP4400: Advanced NVM device selection (ADS) WP4500: RISK analysis (ADS) MRAM from Everspin WP 5000: Radiation Characterization of the DRAM Device Type WP5200: Review of any DRAM radiation test results (IDA) Heavy Ion SEE Test 7
8 Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Tests
9 Tests overview Date Type Facility Memories 11/2015 Heavy-ion SEE RADEF MRAM 4/2016 Heavy-ion SEE RADEF MRAM, DDR3 9/2016 In-situ TID PTB DDR3 FP Days ESTEC , Michalik Slide 9
10 Short Summary of Previous work DDR3 (done in RHM study) TID: Hynix, Samsung: 400 krad (in-situ) Micron: 60 krad (in-situ) SEE: Hynix, Samsung SEE error mechanism with data loss: device SEFI No single-event latch-up, no destructive events FP Days ESTEC , Michalik Slide 10
11 Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Tested devices
12 Tested device types Label Technology Manufacturer Capacity Part number Tests Nan4 DDR3 SDRAM Nanya 4 Gbit NT5CB512M8C N-EK Es1 MRAM Everspin 1 Mbit MR0A08BCYS3 5 Es16 MRAM Everspin 16 Mbit MR4A08BCYS3 5 SEE + TID SEE SEE FP Days ESTEC , Michalik Slide 12
13 Sample preparation DDR3 Heavy-ion SEE test Flip-chip BGA package backside irradiation Thinned to 60 µm Performed by Fraunhofer IOF, Jena In-situ TID test 8 samples soldered to SODIMM FP Days ESTEC , Michalik Slide 13
14 Sample preparation MRAM Heavy-ion SEE tests: 0.8 mm TSOP package Opened by nitric acid etching Soldered to carrier PCB Performed by IDA FP Days ESTEC , Michalik Slide 14
15 Test modes Storage mode: write before irradiation, read after irradiation Read mode: continuous read during irradiation; errors accumulate in DUT Marching mode: during irradiation, immediately rewrite each cell with inverse and verify (read write verify) FP Days ESTEC , Michalik Slide 15
16 Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Test facilities and test equipment
17 Test facility RADEF 9.3 MeV/amu heavy-ion cocktail MRAM: Not all ions used due to time and source availability constraints Ion Energy [MeV] Range [µm] LET [MeV cm 2 mg -1 ] Surface 55 µm 15 N Ne Ar Fe Kr Xe FP Days ESTEC , Michalik Slide 17
18 Test facility PTB Physikalisch-technische Bundesanstalt, Braunschweig The national German metrology institute 2 krad/h (30 rad/min) FP Days ESTEC , Michalik Slide 18
19 Test equipment DDR3 FP Days ESTEC , Michalik Slide 19
20 Test equipment DDR3 for SEE Test FPGA (Xilinx Virtex6) Water cooler DDR3 device (opened) Power switching Custom SODIMM ZIF socket FP Days ESTEC , Michalik Slide 20
21 Test equipment DDR3 TID DUTs Source Lead Steel Water Electrical FP Days ESTEC , Michalik Slide 21
22 Test equipment DDR3 TID SODIMM DUT FPGA (Xilinx Virtex6) Flexible extension FP Days ESTEC , Michalik Slide 22
23 Test equipment DDR3 Source DUTs ML605 Dosimeter Current measurement USB adapter Cooler FP Days ESTEC , Michalik Slide 23
24 Test equipment MRAM Xilinx Zynq-7000 AP SoC FPGA Dual-core ARM Cortex A9 (667 MHz) Integrated dual 12-bit ADC Components: Main board (Avnet MicroZed): Zynq, power supply, Ethernet Interposer (custom PCB): power switching, current measurement DUT carrier (custom PCB): DUT, ID EEPROM, temperature sensor Improvements over DDR3 tester: Quick setup Connection to PC via Ethernet Small footprint FP Days ESTEC , Michalik Slide 24
25 Test equipment MRAM FP Days ESTEC , Michalik Slide 25
26 Test equipment MRAM FP Days ESTEC , Michalik Slide 26
27 Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Test procedures and test results MRAM heavy-ion SEE
28 MRAM SEE Test procedures Test conditions: Test in vacuum without heating/cooling Standard voltage 3.3 V SRAM interface Storage mode, read mode, marching mode Pseudo-random pattern Latch-up switch: 60 ma FP Days ESTEC , Michalik Slide 28
29 MRAM SEE Error classification SEU (SBU or MBU) Stuck bit SEFI no further distinction linear address space Current increase FP Days ESTEC , Michalik Slide 29
30 MRAM SEE Current Current increase observed In steps Latch-up Defined as current > 60 ma Distinction from current increase by arbitrary threshold FP Days ESTEC , Michalik Slide 30
31 MRAM SEE Current increase Red lines: latch-up switch triggered Current increases in steps Current sometimes returns by itself No connection between data errors and current increase FP Days ESTEC , Michalik Slide 31
32 MRAM SEE Latch-up (1 Mbit) Only at highest LET (xenon) Only in read and marching mode FP Days ESTEC , Michalik Slide 32
33 MRAM SEE Latch-up (16 Mbit) In all modes Not at lowest LET (nitrogen) FP Days ESTEC , Michalik Slide 33
34 MRAM SEE Latch-up (comparison) All modes FP Days ESTEC , Michalik Slide 34
35 MRAM SEE Data errors SEUs Static and transient Mostly MBUs (multiple errors in one word) No stuck bits SEFIs Transient only (e.g. address decoder hit) No flux dependence No data error analysis performed for marching mode due to latch-up FP Days ESTEC , Michalik Slide 35
36 MRAM SEE Static SEUs in Read Mode FP Days ESTEC , Michalik Slide 36
37 MRAM SEE Transient SEUs in Read Mode FP Days ESTEC , Michalik Slide 37
38 MRAM SEE SEFIs (16 Mbit) 1-Mbit devices: no useful data, flux too high FP Days ESTEC , Michalik Slide 38
39 MRAM SEE SEFI patterns Often length 256 and start at multiple of 256 Often multiple SEFIs with related start address E. g., 0x070000, 0x0a0000, 0x170000, 0xa70000 Polarity: sometimes mixed, sometimes all-down FP Days ESTEC , Michalik Slide 39
40 Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Test procedures and test results DDR3 heavy-ion SEE
41 DDR3 SEE Test procedures Test conditions: Test in vacuum without heating/cooling 333 MHz Standard voltage 1.5 V Standard refresh rate 7.8 µs Read mode (continuous read during irradiation) Pseudo-random pattern Software conditioning Tests with and without software conditioning Rewrite mode registers, DLL reset, long ZQ calibration FP Days ESTEC , Michalik Slide 41
42 DDR3 SEE Error classification SEU (SBU or MBU) Stuck bit SEFI Row SEFI Column SEFI Device SEFI FP Days ESTEC , Michalik Slide 42
43 DDR3 SEE Results No latch-up No MBUs Low threshold LET for SEUs, stuck bits, row SEFIs, column SEFIs, and device SEFIs Cross sections comparable to other 4-Gbit device types (Hynix, Micron, Samsung) No column SEFIs for Hynix and Samsung FP Days ESTEC , Michalik Slide 43
44 DDR3 SEE SEUs Software conditioning has no effect FP Days ESTEC , Michalik Slide 44
45 DDR3 SEE Stuck bits Software conditioning has no effect FP Days ESTEC , Michalik Slide 45
46 DDR3 SEE Row SEFIs Software conditioning reduces row-sefi sensitivity Row SEFIs often appear in groups of 8 FP Days ESTEC , Michalik Slide 46
47 DDR3 SEE Column SEFIs Software conditioning eliminates column SEFIs Column SEFIs almost always appear in groups of 8 FP Days ESTEC , Michalik Slide 47
48 DDR3 SEE Device SEFIs Software conditioning eliminates device SEFIs (but note error bars) FP Days ESTEC , Michalik Slide 48
49 Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Test procedures and test results DDR3 in-situ TID
50 DDR3 TID Current Unexplained FP Days ESTEC , Michalik Slide 50
51 DDR3 TID Data errors Reported density limited by test equipment Pseudo-random pattern Round-robin write/read in 15-minute intervals 333 MHz Standard refresh interval 7.8 µs FP Days ESTEC , Michalik Slide 51
52 Conclusions MRAM: Current increase, latch-up SEUs, SEFIs DDR3: TID: 400 Gy (40 krad), Hynix: > 4 kgy (400 krad) Severe current increase SEE: Comparable with Hynix, Samsung No latch-up, but device SEFIs FP Days ESTEC , Michalik Slide 52
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