Microelectronics Presentation Days March 2010

Transcription

1 Microelectronics Presentation Days March 2010 FPGA for Space Bernard Bancelin for David Dangla Atmel ASIC BU Aerospace Product Line Everywhere You Are

2 Atmel Radiation Hardened FPGAs Re-programmable (SRAM based technology) No reliability issue SEU hardened Memory points Core cell Flip-Flops, embedded memory, configuration memory and controller No need for SEU mitigation SEL immunity and TID tolerance up to 300 krad Embedded Memory blocks (FreeRAM) Atmel also offers EEPROMs for FPGA configuration 2

3 ATF280F Key Features 280K equivalent ASIC gates 50MHz maximum system clock core-cells (each 2 LUT + 1 DFF) 115 Kbit FreeRAM (900 modules of 32x4 blocks) 1.8V Core / 1.8V and 3.3V I/Os Dedicated LVDS buffers: 8 Rx + 8 Tx Cold-sparing and 3.3V PCI-compliant I/Os ATC18RHA 0.18um technology (same as ATC18RHA ASIC) MCGA 472 (308 User I/O) / MQFP-352 (232 User I/O) Possibility for MQFP-256 (148 User I/O) packages Configuration load integrity check Configuration self-integrity check Boundary scan interface 3

4 Atmel Radiation Hardened FPGAs Layout rules Improved to avoid multiple nodes charge collection during a single heavy ion impact SEU hardened Memory points Core cell Flip-Flops, embedded memory, configuration memory based on radiation hardened Flip-Flops Controller protected by classical TMR Including combinatorial logic and flip-flop of all states machines Clock and reset trees Protected by DMR (resistive isolation path based on N and P isolated path carrying the same signal) Your Design is radiation Hardened by construction No need for SEU/SET mitigation 4

5 Hardened Memory Cell and Isolation Path 5

6 Test Results Single Event Latch-up No SEL detected over all the runs performed and in particular with the runs performed at 1.95V core voltage and 3.6V I/O buffer at LBNL with Xenon and 45 deg tilting angle that corresponds to a LET of 76 MeV/(mg/cm²) and a device under test (DUT) temperature of 125 C, up to fluence of part/cm². Cross section The configuration SEU error cross section per device versus effective LET is derived from the tests performed in UCL, LBNL and RADEF. - Configuration memory SEU saturated cross-section better than per device ( cm² per bit) with a LET threshold around 30MeV at Vcc min. - No SET was recorded with a LET of 43 MeV/(mg/cm²). - SET error cross-section per device about at 60MeV/(mg/cm²). - FreeRAM Asymptotic SEU error cross-section per bit about cm². 6

7 SEU sensitivity of ATF280F configuration bits 7

8 Design Power-on current Design Optimization - Wrong evaluation of power-on current: Random initial configuration induce high power in core cells - Sequential start of configuration memory (final value to be confirmed after full characterization) Routing: speed improvement - Pass gates on local/express buses with lower Ron - 10% improvement New silicon fully functional, characterization in progress 8

9 AT69170E Key Features 4 Mbit Rad Hard EEPROM 512 bytes Pages Standard TWI programming interface FPGA serial configuration interface AT69170E EEPROM Core 3.3V Supply Voltage FP18 Package Memory Controller Endurance: 10K cycles Data retention: 15 years Serial -izer POR TWI Interf TID > 60Krd Programming tools Standalone USB programmer 9

10 Design Tools Front-End 3 years contract signed with MENTOR MENTOR Precision Synthesis - VHDL / Verilog entry - Automatic IDS Macro detection and mapping - On going improvements Back-End ATMEL Figaro IDS - Automated Place & Route - STA - Power Estimator - VHDL / Verilog netlist export with SDF back-annotation - Bitstream generation ATMEL Configurator Programming Tool - ATMEL EEPROM programming 10

11 ATFS450 FPGA Features Joint ATMEL and HIREC development with CNES and JAXA support OSC 150nm SOI process Latch-up free Far more easier SEU/SET hardening (smaller die size) 450K equivalent ASIC gates 152x152 core cells 75 MHz internal performance 3.3V and 1.8V programmable IO and 1.5V array bias voltages 230 cold sparing and PCI Compliant I/O pads Radiation hardened FreeRAM 180 KBits 8 pairs LVDS 240Mbps transceivers and 8 pairs LVDS 240Mbps receivers 8 Global SEU/SET immune Clocks Package MQFPF256 (118 IOs), MQFPF352 (214 IOs) Radiation hardness Heavy ions Latch-up free at LET of 70 MeV/mg/cm² at 125 C SEU/SET free at LET of 64 MeV/mg/cm² Test up to a Total Dose of 100 krad 11

12 Devices Availability AT40KEL040 Now ATF280F Samples Now Engineering Models (after full characterization) - ATF280F-2J-E July ATF280F-KA-E July 2010 Flight Models (QML-Q, QML-V) Nov 2010 ESCC evaluation Jan 2011 ATFS450 1 st samples Nov 2010 Flight Models Jan 2012 AT69170E Prototypes oct 2010 Space Qualification Q

13 ATMEL FPGA suite Improvements Precision Improvements Usage of other macros than FGEN1 Max Fan-Out and Replicate capacitor, fan-in, timing in macro report on number of Core Cell per LPM IO pad registers (Done (2009a.95 upd2 prod) more combinationnal cell in ATF280 than in AT40K BufZ not automaticaly inserted in ATF280 (Done (2009a.95 upd2 prod) GCLKBUF on clock pad over max size ROM generates crash skip unused pins in hierarchical blocks register with enable (FDE) not working (Done (2009a.95 upd2 prod) new wireload model inconsistent timing reports optionnal use of FA, MULT use Carry select adder LPM LPM MUX macro generator not selected some ROM generated with FGEN1 Area report without LPM 13

14 Space FPGA Roadmap Legend AT40K CMOS AT40K SOI Higher integration 2 off AT280 AT280 ATFS450 2 off ATFS450 IDS Design Kit Time scale 14

15 Module 2: Reconfigurable Processor 15

16 Reconfigurable Processor Synoptic 16

17 Reconfigurable Processor Test 17

18 Module2: ATF280F+AT

19 Devices Availability Reconfigurable Processor AT697F+ATF280F Package CQFP352 Samples Dec 2010 Qualification using ESCC (not ECSS) tbd (Q2/2011?) Module with 2xATF280 and 2xAT69170 Package CQFP352 Samples (1Q after AT69170 availability) Q Flight Models Q Some Customer Request for a module with ATF280+AT

20 Higher integration Space FPGA Roadmap Kg Kg 2 off 2500 Kg 1200 Kg Legend AT40K CMOS AT40K SOI NG NG FPGA FPGA CMOS CMOS NG FPGA SOI MCP FPGA 2000 Kg 2 off AT280 AT280 ATFS450 2 off ATFS Kg IDS Design Kit NG DK Time scale 20

21 Questions? Thank You 21