The SpaceWire RTC: Remote Terminal Controller
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1 SpaceWire-SnP Working Group ESTEC, Sept 15 th, 2004 The : Remote Terminal Controller Data Systems Division luca.tunesi@esa.int ESTEC, Sept 15 th, 2004 slide: 1
2 Background: the OPDPS Low/Med. Speed Bus:CAN High Speed Network: SpaceWire Inst. 1 Data Compression High Capacity Memory Inst. 2 V, I, T Acquisition (Monitor) Inst. n Discrete Commands RTC Complex Instrument Complex Instrument SpaceWire RTC Telemetry Formatter/ Encryption Instrument RTC I/O Module (Optional) µp Control Processor DSP Processor ESTEC, Sept 15 th, 2004 slide: 2 Spacecraft Control Bus
3 Background: Network Hierarchy SpaceWire High Speed Network Interconnections among systems Interconnections among modules 1Mbit/s Low Speed Bus Low Data rate Instruments bus CAN Telemetry Collection & Commands distribution Data Rate Sensor Bus TBD (1-wire?) Local Sensors bus Debug and Test at Sub-unit level ESTEC, Sept 15 th, 2004 slide: 3
4 Objective A Smart Component for Dumb Terminals Development of an ASIC SpW Remote Terminal Controller (RTC) for connection of SpaceWire nodes (with or without local intelligence)! It shall be Remotely configurable! It shall implement A bridge SpaceWire- CAN! It shall have Some processing power to work autonomously! It will be used for Simple nodes (I/O Boards, TM/TC boards, sensors, actuators) Intelligent nodes such as processor boards, DPUs, ICUs etc. ESTEC, Sept 15 th, 2004 slide: 4
5 Features (1 st st )! Unit configurable and controlled via SpW link (Remote Control)! SpaceWire I/F as high speed links! FIFO (buffer) I/F! RAM (buffer) I/F! CAN I/F Controller (CANC)! RTC Manager embedded µcontroller (RTM) SpW-SnP! GP-I/O configurable channels Digital commands Pulse commands Digital states ESTEC, Sept 15 th, 2004 slide: 5
6 Features (2 nd nd )! ADC Interface for analogue acquisitions! DAC interface! Host bus I/F! Embedded UARTs! Embedded user s Timers! JTAG port for test purposes (TBC) ESTEC, Sept 15 th, 2004 slide: 6
7 Block Diagram Serial links Discrete commands & Status UART 1 UART 2 GP I/O RTC RTC Remote Terminal Controller TIMER 1 DM (Memory) DAC I/F ADC TIMER 2 JTAG RTM RTC Manager (µc) PM (Memory) ADC I/F DAC SpaceWire Interface FIFO/RAM I/F HOST I/F CANC CAN Controller SpaceWire Links FIFO/RAM PROM µp CAN Bus ESTEC, Sept 15 th, 2004 slide: 7
8 Technology! ASIC Process Implementation in ATMEL Rad-hard 0,18µm CMOS process ESA-ATMEL MPWP Multi-Project Wafer Programme Max gate count 7Mgates Standard-cell ATC18RHA libraries! Radiation Tolerance Functional TID up to 200KRads SEU free cells (>100MeV) Used for all critical memory cells Latch-up immunity to >100MeV ESTEC, Sept 15 th, 2004 slide: 8
9 Preliminary Assessment! Technology (TBC) Pad/Pin count: pads, pins Gate Count: 700K-1M gates Reticule M2 (ATC18RHA95_324) or M3 (ATC18RHA95_404)! Performance SpaceWire 200Mbit/s (2links) CAN 1Mbit/s 115.2Kbit/s Processing power TBD! Power Supply/Consumption 1.8V & 3.3V (TBC) mW WC Power consumption (TBC) ESTEC, Sept 15 th, 2004 slide: 9
10 Work Breakdown Structure ESTEC, Sept 15 th, 2004 slide: 10
11 Time Frame! Invitation to Tender Q1 2004! Negotiation On-going! Kick-off Q4 2004! FPGA Prototype Q3 2005! ASIC Prototypes Q2 2006! ATMEL Standard Production Q (TBC) ESTEC, Sept 15 th, 2004 slide: 11
12 Possible Evolution! Field / Sensor Bus (1-wire? )! Integrated smart Sensors! Integrated diagnostic I/F (JTAG like?)! Other I/Fs (MIL-STD-1553?, Wireless ) ESTEC, Sept 15 th, 2004 slide: 12
13 References I., Philippe Armbruster, On-board Hierarchical Network, SPIE 2003 Barcelona (Sp), 8-10 Sept 2003 II. III. Philippe Armbruster, On-board Payload Data Processing Systems, Technical Dossier on Mapping, TOS-E-1A-DOS-1, Issue 1 Revision F, 06 Feb 2003 ESA/ESTEC/TOS-EDP, SpaceWire Web Site, IV. EMITS: ESTEC, Sept 15 th, 2004 slide: 13
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