16th Microelectronics Workshop Oct 22-24, 2003 (MEWS-16) Tsukuba Space Center JAXA

Transcription

1 16th Microelectronics Workshop Oct 22-24, 2003 (MEWS-16) Tsukuba Space Center JAXA 1 The proposed presentation explores the use of commercial processes, including deep-sub micron process technology, package technology, and COTS products in satellite and satellite launch vehicle applications. To support Aeroflex aggressive product development plans a fab independent business model was selected along with a mind set to leverage leading edge commercial technology in the development of products targeted for satellite applications. jose.martins@aeroflex.com 2

2 Aeroflex Fabless Business Model Technology Requirements Definition Foundry Relationships Device Characterization Library Development Customer Design Circuit Design / Chip Layout Inventory for: Standard Parts Generic Parts Foundry for: New / Future Parts ASICs Wafer Fabrication Circuit Card Assembly Die Packaging and Test Reliability, Failure Analysis Customer Support 3 Aeroflex Technology Roadmap Former UTMC Foundry UTB --- UTD/R --- UTE/R 3µ 1.5µ 1.2µ UTMC s GA/SA Architecture, Design Library, CAD System 3.3/5V Digital CMOS Mixed Signal (3.3/5V) NV (Floating Gate) 1.8/2.5/3.3V Digital CMOS Dense Embedded SRAM Mixed Signal (2.5/3.3V) NV (Flash, Anti-Fuse) UTMC s SA/SC Architecture, Design Library, CAD System 1.8/2.5/3.3V Digital CMOS Dense Embedded SRAM Inherent RadHard Process AMI / Hyundai Commercial Foundry 3.0µ, 1.2µ, 0.6µ, 0.35µ UTMC s SA/SC Architecture, Design Library, CAD System TSMC/WaferTech, Hyundai, NSA/SPL (Nat'l Semi) Commercial Foundry 0.25µ Commercial / Strategic RadHard Module & RHbyDesign TSMC/WaferTech, Hyundai Commercial Foundry 0.18µ GA - Gate Array SA - Structured Array SC - Standard Cell 4

3 Commercial RadHard Module Standard Commercial Process Bulk Wafer Start OP 62 OP 63 OP 64 Standard Acceptance Tests Epi Wafer Start Module Insertion Point OP 62 OP 63 Commercial RadHard Process OP 64 Standard Acceptance Tests MOD OP 1 MOD OP 2 Epi Starting Wafers Non-Invasive Process Module Standard Wafer Acceptance Testing 5 Commercial RadHard Passes > 300 krad(si) Id (A) 1.0E E E E E E E E E E E E-12 Standard AMI Lot X0.6 µm N-Channel Transistor FAIL Leakage Limit PASS Vg (V) Standard Transistor Fails ~3 krad(si) 0 krad 3 krad 10 krad 20 krad 30 krad Id (A) 1.0E E E E E E E E E E E E-12 Commercial RadHardTM Lot , 20X0.6 mm N-Channel Transistor FAIL Leakage Limit PASS 0 krad 50 krad 100 krad 150 krad 200 krad 300 krad 400 krad Vg (V) With Commercial RadHard, Transistor Passes > 300 krad(si) 6

4 Aeroflex UT0.6µm RadHard SEU 1.00E E-06 DFF Error X-Section / Bit (cm -2 ) 1.00E E E E-10 LDFF SDFF Adams 90% Worst Case Geo Error Rate Updated August 1999 DFF 5.0E-8 errors/bit-day LDFF 5.0E-9 errors/bit-day SDFF 1.0E-10 errors/bit-day SEL immune > 128MeV 1.00E LET (MeV-cm 2 /mg) 7 Aeroflex UT0.25µm RadHard SEU SEU Results 1.0E V, Room Temperature Error Cross-Section Per Bit (cm -2 ) 1.0E E E E E-10 DFF LDFF SDFF EDFF Adams 90% Worst Case Geo Error Rate: DFF 1.65E-8 errors/bit-day LDFF 6.74E-9 errors/bit-day SDFF 2.18E-9 errors/bit-day EDFF 1.59E-11 errors/bit-day 1.0E LET (MeV-cm 2 /mg) 8

5 0.25µm Fabless Business Model In Practice Test: Two Technology Characterization Vehicles (TCVs) Classified ASICs: 1.8M Gates, 1.95M Gates, 300K Gates Advance EHF Program Aeroflex Classified Services Radiation Hardness IC Design Expertise Assembly/Test Quality Assurance Wafer Personalization (metal NSA/SPL National Semiconductor TSMC 0.25µ Process Underlayers Test: Two Technology Characterization Vehicles (TCVs) ASICs: 500K Gates NPOESS Program Aeroflex Radiation Hardness IC Design Expertise Assembly/Test Quality Assurance TSMC 0.25µ Process 9 UT8R512K8 / UT8R128K32 SRAM µm Bulk CMOS 4Mbit SRAM Aeroflex design for low power, high speed, and SEU performance Organized as 512K x 8 and 128K x 32 15ns access time, asynchronous operation Both read and write Commercial architecture and compatible pin-out -55 o C to +125 o C LVCMOS inputs and outputs I/O Voltage: 2.5 to 3.3 volts Memory core: 1.8 volts 10

6 UT8R512K8 / UT8R128K32 SRAM µm Bulk CMOS Design Approach Full custom layout Spatial design rules added to the base process to mitigate Single Event Latch-up and improve Dose Rate Response Single Event Upset 12T Memory Cell Redundant latches and flip-flops Total Ionizing Dose CRH Module ( edged transistor design due to the required packing density) Fast Access Time and Low Power Consumption Commercial architecture and layout techniques Pulsed architecture along with 1.8 volt core 11 Aeroflex RadHard LVDS Family 12

7 UT54LVDS031 Quad Driver LVDS driver consists of a current source output which drives a closely-coupled (closelyspaced) differential pair of conductors 340mV nominal differential signals D IN1 D1 D OUT1+ D OUT1- D IN V CC D OUT D IN4 D OUT D OUT4+- D IN2 D2 D OUT2+ D OUT2- EN 4 13 D OUT4- UT54LVDS031 D OUT2-5 DRIVER 12 EN D OUT D OUT3- D IN3 D3 D OUT3+ D IN D OUT3+ D OUT3- GND 8 9 D IN3 D IN4 D4 D OUT4+ D OUT4- EN EN 13 UT54LVDS217/218 Serializer and Deserializer UT54LVDS217 converts 21 bits of CMOS data into three LVDS data streams A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link Every cycle of the transmit clock, 21 bits of input data are sampled and transmitted UT54LVDS218 receiver converts the LVDS data streams back into 21 bits of CMOS data CMOS Input (21) CMOS Parallel to LVDS D1 D2 D3 DATA (LVDS) (140 to 280 Mbps on each LVDS Channel) + R1 - + R1 - + R1 - LVDS to CMOS Parallel CMOS Ouput (21) Transmit Clock PLL D4 CLOCK (LVDS) (20 to 40 MHz) + R1 - PLL Receiver Clock UT54LVDS217 UT54LVDS218 14

8 Microcontrollers 15 UT80CRH196KDS 16-bit Rad-Hard CMOS microcontroller Built using Commercial RadHard TM process technology Total dose greater than 100Krads(Si) Single Event Latch-up Immune LET Threshold around 25MeV-cm 2 /mg Saturated Cross Section is cm 2 /bit Feature Addressable Memory Space Internal RAM (including SFRs) One Time Programmable ROM Maximum Operating Frequency UT80CRH196 64K Kbytes 1024 bytes 0 bytes 20 MHz 16

9 UT80CRH196KDS System Block Diagram UT80CRH /1773 Serial Port Logic Volatile Memory Non Volatile Memory 17 UT54ACS162245S Multipurpose Transceiver 18

10 UT54ACS162245S Multipurpose Transceiver Functional description 16 bit wide bi-directional bus driver Dual bus architecture Separate power and control for Port A and Port B Word (16 bits) and byte (8 bits) control Control signals are 2.5 Volt compatible, 3.3 Volt tolerant Total dose irradiation testing to MIL-STD-883 Method 1019 Intrinsic total dose: 1M rad(si) nominal (wafer lot specific) Latchup immune (LET > 100 MeV-cm 2 /mg) Packaging 48-lead flatpack 3.3V bus to 2.5V bus 2.5V bus to 3.3V bus 19 UT54ACS162245S Multipurpose Transceiver System Block Diagram VDD ON VDD ON 3.3 Volt System Processor Back-plane Interface Logic System Clock (Low Noise) Voltage Translator (3.3V/2.5V) (2.5V/3.3V) 2.5 Volt Memory System 20

11 Aeroflex QCOTS Program Program Goal The Aeroflex QCOTS program aims to bring leading edge, high performance commercial products (COTS) into the space community. By quantifying specific attributes of COTS products, building the product form a homogenous wafer lot of material, and performing in-depth electrical, structural, and radiation hardness assurance analyses, Aeroflex can offer a commercially designed and fabricated product with a quality on par with traditional S level components. 21 Aeroflex QCOTS Program The Approach Quantify (Q) specific attributes of Commercial Off-The-Shelf Product (COTS) for use in spaceborne electronics. Build product out of a homogenous wafer lot of material Guarantee immunity to charge particle induced latchup (>100MeVcm 2 /mg) and quantify charge particle induced upset LET and crosssection on every wafer lot. Guarantee a minimum of 90/90 survival probability to ionizing dose on every wafer lot. Demonstrate reliability for space mission applications (requirement of <10FITs with <1FITs possible). Wafer lot specific life testing, same as QML V (0% PDA, Better than QML V) 22

12 Aeroflex QCOTS Program Benefits of Aeroflex s QCOTS Approach Single Event Latchup Immunity: Guaranteed and tested (on every wafer lot) by Aeroflex Single Event Upset: Quantified cross section and on-set LET evaluation, tested for every wafer lot Total Dose: Wafer lot qualification performed by Aeroflex Reliability: Wafer lot FIT rate evaluation using proven accelerated life-test techniques, 0% PDA allowed for shippable units Manufacturing Flow: Built by Aeroflex, an industry leader in QML manufacturing techniques Standard Product: Sold to an Standard Microcircuit Drawing (SMD) 23 UTXQ512 4M SRAM 4Mbit density Organized 512K x 8 100ns (X=7) and 25ns (X=8 or X=9) access time, asynchronous operation Commercial architecture and compatible pin-out TTL inputs and outputs (100ns, X=7) TTL inputs and outputs (25ns, X=8 or X=9) CMOS outputs (i.e., low and high current specifications) 5 volt operation (100ns product, X=7) - SMD Inputs are not 3.3 volt compatible 3.3 volt operation (25ns product, X=8) - SMD Inputs are not 5 volt tolerant 5 volt operation (25ns product, X=9) - SMD Inputs are not 3.3 volt tolerant Available in military and industrial temperature ranges 24

13 UTXQ512 4M SRAM 25 UT9Q512 4M SRAM Total dose irradiation testing to MIL-STD-883 Method 1019 Intrinsic total-dose: 50K rad(si) nominal (wafer lot specific) Space environment shields to greater than 100Krad(Si) 36-lead surface mount patented UTMC shielded package only SEL Immune >80 MeV-cm 2 /mg (3 per lot testing) LET TH (0.25) ~10 MeV-cm 2 /mg Saturated Cross Section (cm 2 ) per bit ~5.0E-9 <1E-8 error per bit-day (Adams 90% worst case, geosynchronous) 26

14 UT8Q1024K8 8M SRAM 27 UT8Q1024K8 8M SRAM Packaging 44-lead dual cavity ceramic flatpack 4.6 grams Single 3.3+/-10% volt supply (25ns) Average Operating Current, 100% duty cycle, 1MHz Read/Write cycle < 125mA Average Operating Current, 100% duty cycle, 40MHz Read/Write cycle < 180mA CMOS Stand-By Current (Post-Rad, nominal conditions) < 6mA 28

15 UTXQ512K32 16M SRAM MCM 29 UTXQ512K32 SRAM MCM MCM contains four (4) 512K x 8 industrystandard asynchronous SRAMs; the control architecture allows operation as 8, 16, 24, or 32-bit data width TTL inputs and outputs (25ns, X=8 or X=9) CMOS outputs (i.e., low and high current specifications) 3.3 volt operation (25ns product, X=8) Inputs are not 5 volt tolerant 5 volt operation (25ns product, X=9) Inputs are not 3.3 volt tolerant Available in MIL-TEMP and Industrial temperature ranges 30

16 Technology Summary Aeroflex continues to meet our customer s RadHard requirements through commercial foundry technology 6 th year of QML production using our minimally invasive process changes for Commercial and Strategic RadHard environments (0.6µ -AMIS) FIT rates now below 2 RHbyDesign, taking advantage of the inherently radiation hardened characteristics present in commercial submicron processes today (0.25µ TSMC) Exploring 0.13µ RHbyDesign using third party standard cell libraries and commercial foundries Aeroflex s Fab Independent Business Model: Continues to supply needed technologies - mitigating last-time-buy decisions (3.0m, 1.5m, 1.2m, 0.8m; 5V & 3.3V) while delivering Leading-edge, Deep Submicron, Rad-Hard Technology without significant capital equipment investments 31