8. PROGRAMMABLE LOGIC AND MEMORY

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1 Logic & Memory PROGRAMMALE LOGI AND MEMORY Objectives Learn various memory devises and programmable logic devices Learn the method to design logic circuits with programmable logics & memories Introduction logic devices (PLDs) An integrated circuit with internal logic gates and/or connections that can be changed by a programming process Memory: RAM (randomaccess memory) and ROM (readonly memory) logic array (PLA) array logic (PAL) logic devices (PLD: Altera) 5 Field programmable gate array (FPGA: ilinx & Actel) RandomAccess Memory A collection of binary storage cells together with associated circuits needed to transfer information to or from any directed location, with the access taking the same time regardless of the location (cf serial memory) Word/ yte K(kilo), M(mega), G(giga) Address Read Write hip select k input n Memory unit k words n bits/word n output Memory address inary Decimal Memory contents lock diagram of Memory ontents of a 6 Memory DongSeog Han

2 Logic & Memory ontrol to a Memory hip hip select (S), Memory operation None Write to select word Read from selected word Example ypress k Static RAM Features 55, 7 ns access times MOS for optimum speed/power Easy memory expansion with /E, E, and /OE features TTLcompatible inputs and outputs Automatic powerdown when deselected () Write & Read Operation Write steps Apply the binary address to the address line Apply the data bits to the data input lines Activate the Write input DongSeog Han

3 Logic & Memory Write cycle time ( t W ) : the maximum time from the application of the address to the completion of all internal memory operations required to store a word Read steps Apply the binary address to the address lines Activate the Read input Read cycle time( R t ): the maximum time from the application of the address to the appearance of the data at the Output DongSeog Han

4 Logic & Memory () Properties of Memory Static RAM (SRAM): consists of internal latches Dynamic RAM (DRAM): stores the binary data in the form of electric charges on capacitors RAM Integrated ircuits () asic RAM Structure Static S R RAM it Slice Model Word select Word select n In The circuitry associated with a single bit position of a set of RAM words S R S R S R Word select Word select Word select n In Out it Write Logic it Logic diagram Read Logic Out DongSeog Han

5 Logic & Memory 5 6Word by it RAM hip A A A A Input Memory Enable 6x RAM Output A A A A to6 Decoder 5 Input In Out it Output Symbol hip lock diagram Threestate uffers IN EN OUT EN IN OUT HiZ Allows construction of a multiplexer with an arbitrary number of inputs Threestate buffers forming a multiplexed line OL(output line) (S) IN EN IN EN OL EN EN IN IN OL (S) (/S) HiZ DongSeog Han

6 Logic & Memory 6 () oincident ion A RAM Using a Array Row Decoder A A to Decoder Row select logic In Out logic In Out logic In Out logic In Out Read/ Write it Read/ Write it Read/ Write it Read/ Write it input input olumn decoder olumn select to Decoder with enable Enable output output A hip select Symbol for a 6K RAM hip 6k RAM Input Address hip 6 S Output DongSeog Han

7 Logic & Memory 7 Array of RAM Is A 56K RAM 7 6 Address Lines 5 Input Memory enable Read/W rite to Decoder EN 6 6k RAM S 65,56 6k RAM S 65,57,7 6k RAM S,796,67 6k RAM S 96,66, Output A 6K 6 RAM 6 Input Lines Address 6 hip 6 6k RAM S 6k RAM 6 S 6 Output Lines DongSeog Han

8 Logic & Memory 5 ReadOnly Memory (ROM) A device in which permanent binary information is stored (ROM/PROM/EPROM) lock diagram of ROM k inputs (address) k n outputs (data) n ROM Internal Logic of a K ROM I I I I I 5to Decoder 9 A7 A6 A5 A A A A A Example I I I I I A7 A6 A5 A A A A A I I I I I 5to Decoder 9 Fuse intact Fuse blown A7 A6 A5 A A A A A DongSeog Han

9 Logic & Memory 9 Application Design of a combinational logic Design a squarer for a bit input number (a) Truth table A A A 5 (b) Implementation A A A ROM 5 Decimal A A A 5 6 Logic Array (PLA) asic configuration of PLDs ROM (PROM) Fixed AND array (Decoder) onnections OR array array logic (PAL) onnections AND array Fixed OR array logic array (PLA) onnections AND array onnections OR array DongSeog Han

10 Logic & Memory Example PLA with three inputs, four product terms, and two outputs F A A A, F A A A A Fuse intact Fuse blown A A A F F A A A Product term PLA program table A F(T) F() T(True) (omplement) (OPEN) Example Implement the following two oolean functions with a PLA F( A,, ) m(,,,), F ( A,, ) m (,5,6,7) A F A A F A A A F A A A F A A A A A A PLA programming table Pro duct () (T) A term F F DongSeog Han

11 Logic & Memory 7 Array Logic Devices A PLD with a fixed OR array and programmable AND array Example A D Product term AND gates inputs A A' ' ' D D' WW' A A' ' ' D D' WW' All fuses intact (always=) Fuse intact Fuse blown W Y Z Produxt Term AND A D W W A ' A' ' D A Y A' D D ' D' Z W A ' D' A' ' ' D ' DongSeog Han

12 Logic & Memory VLSI Logic Devices Three ways of designing VLSI circuits Fullcustom design Standard cell design Gate array PLDs developed by using VLSI technology Altera MA7 PLDs: Use the EEPROM floatinggate technology Actel AT FPGAs: Use a gatearraylike structure ilinx DongSeog Han