SYSTEM SPECIFICATIONS USING VERILOG HDL. Dr. Mohammed M. Farag

Transcription

1 SYSTEM SPECIFICATIONS USING VERILOG HDL Dr. Mohammed M. Farag

2 Static Random Acce Memory, SRAM SRAM : ue a imple bitable circuit to hold a data bit Three tate: hold, write, and read operation Acce tranitor (NMOS) provide W/R operation (a) 6T Acce tranitor Figure 13.1 General SRAM (b) 4T with poly reitor Figure 13.2 CMOS SRAM circuit

3 SRAM (1/2) Write 1: in wort cae, V 1 = 0, V 2 = V DD (β A /β n = 2) Why?? ( W / L) ( W / L) na n (13.1) Figure T SRAM deign parameter (a) Write 1 operation Static Noie Margin: immunity the coupled electromagnetic ignal (noie) (b) Reitor model Figure 13.4 Butterfly plot Figure 13.5 Writing to an SRAM

4 SRAM (2/2) S: Source D: Drain S D D Figure 13.7 A 2-port CMOS SRAM S Figure 13.6 Example of a baic 6-T SRAM layout Figure SRAM group

5 Outline The Static RAM SRAM Array Dynamic RAM ROM Array Logic Array

6 SRAM Array (1/4) m N 2 Figure 13.9 High-level view of an SRAM Figure Cell arrangement in a core region Figure Central SRAM block architecture Figure Row driver circuit

7 SRAM Array (2/4) Figure Column MUX/DeMUX network for 8-bit word Figure Baic addreing cheme Figure Logic 1 column driver Figure Addre latch circuit

8 SRAM Array (3/4) Figure 3.17 Pre-charge and I/O circuit for a ingle column

9 SRAM Array (4/4) Figure 3.18 Expanded view of column circuitry Figure Write circuitry example

10 Sening Operation Figure 3.20 Example of a ening cheme for the read operation (a) Circuit diagram (b) Current flow Figure 3.21 Single-ended differential amplifier v d ( v v ) (13.5) v out Av d A( v v ) (13.6) I SS I I D1 D2 (13.7) Figure 3.22 Dual-amplifier cheme for the ene amplifier network

11 An example: A Drowy SRAM in3 in2 in1 in0 WE pre_clk Write Circuit Precharge Write Circuit BL0 BL0' BL1 BL1' Precharge Write Circuit Write Circuit BL2 BL2' BL3 BL3' Precharge Precharge 1 V dd0 drowy0 0 WL0 1 V dd1 drowy1 0 WL1 1 V dd2 drowy2 0 WL2 1 V dd3 drowy3 0 WL3 V dd V drowy (1.8v) (0.36v) Sene Amp. Sene Amp. Sene Amp. Sene Amp. Read dec_clk a0 a1 2 to 4 Addre decoder out0 out1 out2 out3

12 Outline The Static RAM SRAM Array Dynamic RAM ROM Array Logic Array

13 DRAM (1/3) Dynamic RAM (DRAM) Smaller than SRAM Higher denity torage array A the central ytem Q CV (13.8) memory in microcomputer For writing 1, ytem V V max VDD VTn (13.9) Require more peripheral Qmax C ( VDD circuitry VTn ) (13.10) (a) Write operation Figure T DRAM (b) Hold Figure 3.24 Write and hold operation in a DRAM

14 DRAM (2/3) Charge Leakage: When V G < V T, a MOSFET i cutoff but till admit dq I L (13.11) mall dt leakage current I L C dv dt (13.12) Figure 3.25 Charge leakage in a DRAM I L C V t (13.13) t h C t I L V (13.14) (hold time or retention time) t h (13.15) (I L =1 na, C =50 ff, and V =1 V) f refreh 1 2t h (13.16) (refreh frequency) Figure 3.26 Refreh operation ummary

15 DRAM (3/3) Figure 3.28 A DRAM uing a trench capacitor Figure 3.26 Read operation in a DRAM Q C V (13.17) Q C V f C bit V f (13.18) V f C C C bit V (13.19) Figure Viualization of tacked capacitor tructure

16 DRAM Array and Peripheral Circuit

17 Divided-Word Line Architecture Figure Baic for a divided-word line architecture RAM layout Figure Logic for a DWL deign

18 Outline The Static RAM SRAM Array Dynamic RAM ROM Array Logic Array

19 ROM Figure Logic diagram for a NOR-baed ROM Figure Map for ROM layout Figure ROM array uing peudo-nmos circuitry Figure ROM layout baed on FET map

20 Uer-Programmable ROM Electrically-eraable EPROM (E 2 PROM) are ued to tore the BIOS code in PC, and allow the uer to update (a) Symbol (a) Normal V Tn tate (b) Increaed V Tn,H tate (b) Structure Figure Logic diagram for a NOR-baed ROM Figure Floating-gate MOSFET

21 E 2 PROM Figure A E 2 PROM word uing floating-gate nfet Figure Fowler-Nordheim tunnelling Figure Programming a floating-gate FET Figure EEPROM with write line

22 Outline The Static RAM SRAM Array Dynamic RAM ROM Array Logic Array

23 Programmable Logic Array, PLA (1/2) Figure Structure of an AND-OR PLA Figure Logic gate diagram of the PLA

24 Programmable Logic Array, PLA (2/2) (a) AND-OR logic Figure A dynamic CMOS PLA baed on NOR gate (b) NOR-baed logic Figure NOR-gate PLA logic Figure Generic NOR-baed logic plane

25 Gate Array (a) Gate array baed (a) Structure (b) Metal-active (c) Metal-metal (b) NOR3 gate wiring Figure NOR-gate PLA logic Figure Tranitor arrangement in a gate array