FPGA 101. Field programmable gate arrays in action
|
|
|
- Solomon Howard
- 5 years ago
- Views:
Transcription
1 FPGA 101 Field programmable gate arrays in action
2 About me Karsten Becker Head of Scientists PhD FPGA Architecture 2
3 What is an FPGA Programmable Logic
4 Programmable logic (LUT) A B X A B Y
5 Programmable logic (LUT) A B X X Y C Z A B Y
6 Programmable logic (LUT) A B X X Y C Z A B Y
7 Registers Logic Reg Logic Reg Reg Logic
8 FPGA vs CPU Time A CPU B C Area/Frequency FPGA A C B
9 Fabric Composed of Hard blocks Lookup tables DSP Units Flip-flops Multiplier Multiplexer Block RAM Routing resources High-speed IO Clock Management CPUs Carry Logic Memory controller Shift-register ADC/DACs
10 Cool FPGA Projects Borgventilator Pixel transformation to polar coordinates Transmission as 8b10 coding Gamma correction Precise timing Go to: Das Labor (Hackerspace) somewhere here
11 Cool FPGA Projects Borgventilator Pixel transformation to polar coordinates Transmission as 8b10 coding Gamma correction Precise timing Go to: Das Labor (Hackerspace) somewhere here
12 Cool FPGA Projects HDMI Overlay Detect HDMI Sync signal Encrypt Overlay Select overlay stream vs content stream Does not decrypt content stream! See
13 Programming High Level tools Matlab Simulink, C to HDL generators, OpenCL to HDL generators Code generation Hardware Description Language VHDL, Verilog, MyHDL, PSHDL Synthesis/Mapping Netlist Place&Route Configuration file
14 Code Example (counter) VHDL library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MyFirstModule is port ( clk : in std_logic; rst : in std_logic ); end; architecture pshdlgenerated of MyFirstModule is signal counter : unsigned(11 downto 0); begin process(clk) begin if RISING_EDGE(clk) then if rst = '1' then counter <= (others => '0'); else counter <= (counter + 1); end if; end if; end process; end; PSHDL module MyFirstModule{ register uint<12> counter=counter+1; } Verilog module counter ( out, clk, reset ); output [7:0] out; input clk, reset; reg [7:0] out; clk) if (reset) begin out <= 8'b0 ; end else begin out <= out - 1; end endmodule
15 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
16 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
17 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
18 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
19 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
20 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
21 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
22 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
23 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
24 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
25 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
26 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
27 Pipelining Calculate (A+B)*(C+D)+10 A B A+B +10 C D C+D Every Clock the data proceeds one step
28 (High-speed) IO Tons of GPIO! Toggle frequency as high as fabric frequency Speeds of up to 400->800 MBit/s with shift registers Some dedicated very high speed transceiver 1->25 GB/s Very detailed control of characteristics
29 CPUs CPUs are good at things that don't repeat very often Large complex pieces of SW like operating system, network stack or dynamic memory allocation quick turnaround times during development
30 Combining CPU and FPGA Connect via bus/memory interface on same PCB Soft CPU realized in fabric Hard CPU realized in silicon on FPGA die
31 Accelerating parts of application Start with a pure SW implementation Measure performance / identify bottle-necks Translate expensive part to HDL
32 Discrete wavelet transformation Used by JPEG2000 Applied to color channels of pictures 2D wavelet = 1D wavelet horizontal + 1D wavelet vertical
33 0 Cache Miss Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Horizontal DWT
34 0 1 Cache Hit Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Horizontal DWT
35 0 1 2 Cache Hit Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Horizontal DWT
36 Cache Hit Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Horizontal DWT
37 Cache Hit Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Horizontal DWT
38 Cache Hit Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Horizontal DWT
39 0 Cache Miss Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Vertical DWT
40 Cache Miss Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Vertical DWT
41 Cache Miss Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Vertical DWT
42 Cache Miss Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Vertical DWT
43 Cache Miss Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Vertical DWT
44 Cache Miss Px9 Px8 Px7 Px6 Px5 Px4 Px3 Px2 Px1 (Px7+Px9)* k1+px8 (Px5+Px7)* k1+px6 (Px3+Px5)* k1+px4 (Px1+Px3)* k1+px2 (R2+R3)* k2+px5 (R1+R2)* k2+px3 Vertical DWT
45 Px1 Px2 Px3 Px4 Px5 Px6 Px7 Px8 Px9 (Px1+Px3)* k1+px2 (Px3+Px5)* k1+px4 (Px5+Px7)* k1+px6 (Px7+Px9)* k1+px8 (R1+R2)* k2+px3 (R2+R3)* k2+px5 FPGA Px1 Px2 Px3 Px4 Px5 Px6 Px7 Px8 Px9 (Px1+Px3)* k1+px2 (Px3+Px5)* k1+px4 (Px5+Px7)* k1+px6 (Px7+Px9)* k1+px8 (R1+R2)* k2+px3 (R2+R3)* k2+px5 Block RAM (1 Line) Horizontal DWT Vertical DWT
46 DWT Summary 1D Horizonal CPU perfect cache hits due to prefetch -> very fast 1D Vertical CPU near always cache miss -> significant slow down FPGA Linear read -> 2 lines latency -> linear full memory speed
47 Tech guide x86 Gpu Dsp Fpga µc Embed Maybe Hard Easy Easy Easy Low power Unusual Nope Sometimes Sometimes Yes Float op Good Excellent Excellent Possible Nope Int op Excellent Excellent Excellent Excellent Mediocore Control flow Excellent Challenging Fair Challenging Excellent IO Mediocore Nope Ok Ginormous Ok Pipelining Nope Nope Nope Yes Nope Programmability Easy Medium Medium Challenging Easy Timing control Medium What? Fair Excellent Fair
48 Vendor Overview Xilinx / Altera Actel (microsemi) Kind of the same Low Power High Performance High reliability High Bandwidth Lattice Biggest 2 on the market Low Power Decent tooling Cheap!
49 Vendor Overview Xilinx / Altera Actel (microsemi) Kind of the same Low Power High Performance High reliability High Bandwidth Lattice Biggest 2 on the market Low Power Decent tooling Cheap! Most expensive Xilinx: EUR Most expensive Altera: EUR (3 pieces min order)
50 Hacker friendly Boards Actel Altera Xilinx Cheap PSHDL Board ~3x DE0-Nano 70 BEMICRO CV 40 Papilio One 47 (Spartan 3) Mojo V3 54 (Spartan 6) XuLA2-LX Powerful Igloo 2 boards Cyclone 5 Arria Artix/Kintex/Virtex SoC SmartFusion2 Starter Kit 295 SmartFusion Starter Kit 100 EBV SoCrates 359 MicroZedBoard ~200 Parallela 85 CPU +FPGA Datenkrake ~95 Logi (Kickstarter)
51 Thanks, questions? For infos about the PSHDL board, visit: boards.pshdl.org Join the workshop on Sunday 9pm Hall F
Readings: Storage unit. Can hold an n-bit value Composed of a group of n flip-flops. Each flip-flop stores 1 bit of information.
Registers Readings: 5.8-5.9.3 Storage unit. Can hold an n-bit value Composed of a group of n flip-flops Each flip-flop stores 1 bit of information ff ff ff ff 178 Controlled Register Reset Load Action
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
Field Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
FPGA briefing Part II FPGA development DMW: FPGA development DMW:
FPGA briefing Part II FPGA development FPGA development 1 FPGA development FPGA development : Domain level analysis (Level 3). System level design (Level 2). Module level design (Level 1). Academical focus
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses
Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single
VHDL simulation and synthesis
VHDL simulation and synthesis How we treat VHDL in this course You will not become an expert in VHDL after taking this course The goal is that you should learn how VHDL can be used for simulation and synthesis
Sign here to give permission for your test to be returned in class, where others might see your score:
EEL 4712 Midterm 2 Spring 216 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)
Field Program mable Gate Arrays
Field Program mable Gate Arrays M andakini Patil E H E P g r o u p D H E P T I F R SERC school NISER, Bhubaneshwar Nov 7-27 2017 Outline Digital electronics Short history of programmable logic devices
Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
EITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Introduction to FPGA design Rakesh Gangarajaiah Rakesh.gangarajaiah@eit.lth.se Slides from Chenxin Zhang and Steffan Malkowsky WWW.FPGA What is FPGA? Field
CSE 260 Introduction to Digital Logic and Computer Design. Exam 1. Your name 2/13/2014
CSE 260 Introduction to Digital Logic and Computer Design Jonathan Turner Exam 1 Your name 2/13/2014 1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C +D)(B+D ) directly (do not
FPGAs in a Nutshell - Introduction to Embedded Systems-
FPGAs in a Nutshell - Introduction to Embedded Systems- Dipl.- Ing. Falk Salewski Lehrstuhl Informatik RWTH Aachen salewski@informatik.rwth-aachen.de Winter term 6/7 Contents History FPGA architecture
DIY soft-core up Microprocessor design using an FPGA made simple. Jim Brakefield
DIY soft-core up Microprocessor design using an FPGA made simple Jim Brakefield Introduction FPGAs: digital circuit with its resources connected by programmable/configurable wiring up: mechanism to sequentially
Digital System Construction
Digital System Construction FYSIKUM Lecture 4: More VHDL, memory, PRNG Arithmetic Memories Pipelines and buffers Pseudorandom numbers IP core generation in Vivado Introduction to Lab 3 Digital Systemkonstruktion
CDA 4253 FPGA System Design Op7miza7on Techniques. Hao Zheng Comp S ci & Eng Univ of South Florida
CDA 4253 FPGA System Design Op7miza7on Techniques Hao Zheng Comp S ci & Eng Univ of South Florida 1 Extracted from Advanced FPGA Design by Steve Kilts 2 Op7miza7on for Performance 3 Performance Defini7ons
FSM Components. FSM Description. HDL Coding Methods. Chapter 7: HDL Coding Techniques
FSM Components XST features: Specific inference capabilities for synchronous Finite State Machine (FSM) components. Built-in FSM encoding strategies to accommodate your optimization goals. You may also
Luleå University of Technology Kurskod SMD152 Datum Skrivtid
Luleå University of Technology Kurskod SMD152 Datum 2003-10-24 Skrivtid 9.00 13.00 1 Manual synthesis (10 p, 2 p each) Here you are given five different VHDL models. Your task is to draw the schematics
VHDL VS VERILOG.
1 VHDL VS VERILOG http://www.cse.cuhk.edu.hk/~mcyang/teaching.html 2 VHDL & Verilog They are both hardware description languages for modeling hardware. They are each a notation to describe the behavioral
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
Introduction to Field Programmable Gate Arrays
Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Historical introduction.
Sequential Statement
Sequential Statement Sequential Logic Output depends not only on current input values but also on previous input values. Are building blocks of; Counters Shift registers Memories Flip flops are basic sequential
Laboratory Exercise 3
Laboratory Exercise 3 Latches, Flip-flops, and egisters The purpose of this exercise is to investigate latches, flip-flops, and registers. Part I Altera FPGAs include flip-flops that are available for
TSEA44 - Design for FPGAs
2015-11-24 Now for something else... Adapting designs to FPGAs Why? Clock frequency Area Power Target FPGA architecture: Xilinx FPGAs with 4 input LUTs (such as Virtex-II) Determining the maximum frequency
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec06-FPGA Page 1 Outline What are FPGAs? Why use FPGAs (a short history
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
Chapter 5: ASICs Vs. PLDs
Chapter 5: ASICs Vs. PLDs 5.1 Introduction A general definition of the term Application Specific Integrated Circuit (ASIC) is virtually every type of chip that is designed to perform a dedicated task.
Outline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Outline What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic
Introduction to VHDL Design on Quartus II and DE2 Board
ECP3116 Digital Computer Design Lab Experiment Duration: 3 hours Introduction to VHDL Design on Quartus II and DE2 Board Objective To learn how to create projects using Quartus II, design circuits and
ESL design with the Agility Compiler for SystemC
ESL design with the Agility Compiler for SystemC SystemC behavioral design & synthesis Steve Chappell & Chris Sullivan Celoxica ESL design portfolio Complete ESL design environment Streaming Video Processing
INTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
CS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory
CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits
SP3Q.3. What makes it a good idea to put CRC computation and error-correcting code computation into custom hardware?
Part II CST: SoC D/M: Quick exercises S3-S4 (examples sheet) Feb 2018 (rev a). This sheet contains short exercises for quick revision. Please also look at past exam questions and/or try some of the longer
Accelerate FPGA Prototyping with
Accelerate FPGA Prototyping with MATLAB and Simulink September 21 st 2010 Stephan van Beek Senior Application Engineer 1 From Idea to Implementation DESIGN Algorithm Development MATLAB Simulink Stateflow
Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
Advanced FPGA Design. Jan Pospíšil, CERN BE-BI-BP ISOTDAQ 2018, Vienna
Advanced FPGA Design Jan Pospíšil, CERN BE-BI-BP j.pospisil@cern.ch ISOTDAQ 2018, Vienna Acknowledgement Manoel Barros Marin (CERN) lecturer of ISOTDAQ-17 Markus Joos (CERN) & other organisers of ISOTDAQ-18
Control Unit: Binary Multiplier. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN
Control Unit: Binary Multiplier Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Example: Binary Multiplier Two versions Hardwired control Microprogrammed
Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE
Qsys and IP Core Integration
Qsys and IP Core Integration Stephen A. Edwards (after David Lariviere) Columbia University Spring 2016 IP Cores Altera s IP Core Integration Tools Connecting IP Cores IP Cores Cyclone V SoC: A Mix of
Digital Integrated Circuits
Digital Integrated Circuits Lecture 9 Jaeyong Chung Robust Systems Laboratory Incheon National University DIGITAL DESIGN FLOW Chung EPC6055 2 FPGA vs. ASIC FPGA (A programmable Logic Device) Faster time-to-market
FPGA. Logic Block. Plessey FPGA: basic building block here is 2-input NAND gate which is connected to each other to implement desired function.
FPGA Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of transistor or as complex as that of a microprocessor. It can used to implement different
Method We follow- How to Get Entry Pass in SEMICODUCTOR Industries for 3rd year engineering. Winter/Summer Training
Method We follow- How to Get Entry Pass in SEMICODUCTOR Industries for 3rd year engineering Winter/Summer Training Level 2 continues. 3 rd Year 4 th Year FIG-3 Level 1 (Basic & Mandatory) & Level 1.1 and
Hardware Design with VHDL PLDs IV ECE 443
Embedded Processor Cores (Hard and Soft) Electronic design can be realized in hardware (logic gates/registers) or software (instructions executed on a microprocessor). The trade-off is determined by how
VHDL And Synthesis Review
VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are read-only
Schedule. ECE U530 Digital Hardware Synthesis. Rest of Semester. Midterm Question 1a
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 8, 2006 Midterm Average: 70 Lecture 16: Midterm Solutions Homework 6: Calculator Handshaking HW 6: Due Wednesday, November
Digital Design with SystemVerilog
Digital Design with SystemVerilog Prof. Stephen A. Edwards Columbia University Spring 25 Synchronous Digital Design Combinational Logic Sequential Logic Summary of Modeling Styles Testbenches Why HDLs?
FPGAs: FAST TRACK TO DSP
FPGAs: FAST TRACK TO DSP Revised February 2009 ABSRACT: Given the prevalence of digital signal processing in a variety of industry segments, several implementation solutions are available depending on
Embedded Systems: Hardware Components (part I) Todor Stefanov
Embedded Systems: Hardware Components (part I) Todor Stefanov Leiden Embedded Research Center Leiden Institute of Advanced Computer Science Leiden University, The Netherlands Outline Generic Embedded System
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
ECE 645: Lecture 1. Basic Adders and Counters. Implementation of Adders in FPGAs
ECE 645: Lecture Basic Adders and Counters Implementation of Adders in FPGAs Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 5, Basic Addition and Counting,
Lecture 3: Modeling in VHDL. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware
08 - Address Generator Unit (AGU)
October 2, 2014 Todays lecture Memory subsystem Address Generator Unit (AGU) Schedule change A new lecture has been entered into the schedule (to compensate for the lost lecture last week) Memory subsystem
Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany
Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany 2013 The MathWorks, Inc. 1 Agenda Model-Based Design of embedded Systems Software Implementation
FPGA How do they work?
ent FPGA How do they work? ETI135, Advanced Digital IC Design What is a FPGA? Manufacturers Distributed RAM History FPGA vs ASIC FPGA and Microprocessors Alternatives to FPGAs Anders Skoog, Stefan Granlund
FPGA for Software Engineers
FPGA for Software Engineers Course Description This course closes the gap between hardware and software engineers by providing the software engineer all the necessary FPGA concepts and terms. The course
Lecture 4: Modeling in VHDL (Continued ) EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 4: Modeling in VHDL (Continued ) Sequential Statements Use Process process (sensitivity list) variable/constant declarations Sequential Statements end process; 2 Sequential
Overview. CSE372 Digital Systems Organization and Design Lab. Hardware CAD. Two Types of Chips
Overview CSE372 Digital Systems Organization and Design Lab Prof. Milo Martin Unit 5: Hardware Synthesis CAD (Computer Aided Design) Use computers to design computers Virtuous cycle Architectural-level,
Basic FPGA Architectures. Actel FPGAs. PLD Technologies: Antifuse. 3 Digital Systems Implementation Programmable Logic Devices
3 Digital Systems Implementation Programmable Logic Devices Basic FPGA Architectures Why Programmable Logic Devices (PLDs)? Low cost, low risk way of implementing digital circuits as application specific
Programmable Logic Devices FPGA Architectures II CMPE 415. Overview This set of notes introduces many of the features available in the FPGAs of today.
Overview This set of notes introduces many of the features available in the FPGAs of today. The majority use SRAM based configuration cells, which allows fast reconfiguation. Allows new design ideas to
Graphics: Alexandra Nolte, Gesine Marwedel, Universität Dortmund. RTL Synthesis
Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Universität Dortmund RTL Synthesis Purpose of HDLs Purpose of Hardware Description Languages: Capture design in Register Transfer Language form i.e. All
VERILOG HDL. 1 ENGN3213: Digital Systems and Microprocessors L#5-6
VERILOG HDL 1 ENGN3213: Digital Systems and Microprocessors L#5-6 Some Reference Material (mostly advanced) \vspace{10mm} http://engnet.anu.edu.au/decourses/engn3213/documents/verilog/ VerilogIntro SASAKI.pdf
Outline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?
Outline EECS 5 - Components and Design Techniques for Digital Systems Lec Putting it all together -5-4 David Culler Electrical Engineering and Computer Sciences University of California Berkeley Top-to-bottom
ECE 699: Lecture 9. Programmable Logic Memories
ECE 699: Lecture 9 Programmable Logic Memories Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections: RAM HDL Coding Techniques ROM
In our case Dr. Johnson is setting the best practices
VHDL Best Practices Best Practices??? Best practices are often defined by company, toolset or device In our case Dr. Johnson is setting the best practices These rules are for Class/Lab purposes. Industry
VHDL for Logic Synthesis
VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for synthesis General guidelines for hardware designers This lecture includes the content from: Nitin Yogi, Modelling for Synthesis
FPGA design with National Instuments
FPGA design with National Instuments Rémi DA SILVA Systems Engineer - Embedded and Data Acquisition Systems - MED Region ni.com The NI Approach to Flexible Hardware Processor Real-time OS Application software
A SIMULINK-TO-FPGA MULTI-RATE HIERARCHICAL FIR FILTER DESIGN
A SIMULINK-TO-FPGA MULTI-RATE HIERARCHICAL FIR FILTER DESIGN Xiaoying Li 1 Fuming Sun 2 Enhua Wu 1, 3 1 University of Macau, Macao, China 2 University of Science and Technology Beijing, Beijing, China
FPGA Implementation and Validation of the Asynchronous Array of simple Processors
FPGA Implementation and Validation of the Asynchronous Array of simple Processors Jeremy W. Webb VLSI Computation Laboratory Department of ECE University of California, Davis One Shields Avenue Davis,
Programmable Logic. Simple Programmable Logic Devices
Programmable Logic SM098 Computation Structures - Programmable Logic Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL architectures Implements
Xilinx ASMBL Architecture
FPGA Structure Xilinx ASMBL Architecture Design Flow Synthesis: HDL to FPGA primitives Translate: FPGA Primitives to FPGA Slice components Map: Packing of Slice components into Slices, placement of Slices
Lecture 38 VHDL Description: Addition of Two [5 5] Matrices
![Lecture 38 VHDL Description: Addition of Two [5 5] Matrices](/thumbs/83/88753861.jpg "Lecture 38 VHDL Description: Addition of Two [5 5] Matrices")
Lecture 38 VHDL Description: Addition of Two [5 5] Matrices -- First, write a package to declare a two-dimensional --array with five elements library IEEE; use IEEE.STD_LOGIC_1164.all; package twodm_array
ECE 545 Lecture 17 RAM. George Mason University
ECE 545 Lecture 17 RAM George Mason University Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques [ UG687 (v 14.5) March 20, 2013 ] Sections:
ESE532: System-on-a-Chip Architecture. Today. Message. Graph Cycles. Preclass 1. Reminder
ESE532: System-on-a-Chip Architecture Day 8: September 26, 2018 Spatial Computations Today Graph Cycles (from Day 7) Accelerator Pipelines FPGAs Zynq Computational Capacity 1 2 Message Custom accelerators
2015 Paper E2.1: Digital Electronics II
s 2015 Paper E2.1: Digital Electronics II Answer ALL questions. There are THREE questions on the paper. Question ONE counts for 40% of the marks, other questions 30% Time allowed: 2 hours (Not to be removed
Laboratory Exercise 8
Laboratory Exercise 8 Memory Blocks In computer systems it is necessary to provide a substantial amount of memory. If a system is implemented using FPGA technology it is possible to provide some amount
HIGH-PERFORMANCE RECONFIGURABLE FIR FILTER USING PIPELINE TECHNIQUE
HIGH-PERFORMANCE RECONFIGURABLE FIR FILTER USING PIPELINE TECHNIQUE Anni Benitta.M #1 and Felcy Jeba Malar.M *2 1# Centre for excellence in VLSI Design, ECE, KCG College of Technology, Chennai, Tamilnadu
yamin/
http://cis.k.hosei.ac.jp/ yamin/ Verilog HDL p.1/76 HDL Verilog HDL IEEE Standard 1364-1995 (Verilog-1995) IEEE Standard 1364-2001 (Verilog-2001) VHDL VHSIC HDL IEEE Standard 1076-1987 AHDL Altera HDL
CCE 3202 Advanced Digital System Design
CCE 3202 Advanced Digital System Design Lab Exercise #2 This lab exercise will show you how to create, synthesize, and test a 3-bit ripple counter. A ripple counter is simply a circuit that outputs the
Latch Based Design (1A) Young Won Lim 2/18/15
Latch Based Design (1A) Copyright (c) 2015 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any
FPGA Technology and Industry Experience
FPGA Technology and Industry Experience Guest Lecture at HSLU, Horw (Lucerne) May 24 2012 Oliver Brndler, FPGA Design Center, Enclustra GmbH Silvio Ziegler, FPGA Design Center, Enclustra GmbH Content Enclustra
COVER SHEET: Total: Regrade Info: 7 (6 points) 2 (10 points) 9 (5 points) 8 (12 points) 12 (5 points) 11 (25 points)
EEL 4712 Midterm 3 Spring 2012 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
Early Models in Silicon with SystemC synthesis
Early Models in Silicon with SystemC synthesis Agility Compiler summary C-based design & synthesis for SystemC Pure, standard compliant SystemC/ C++ Most widely used C-synthesis technology Structural SystemC
ECE 545: Lecture 11. Programmable Logic Memories
ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Memory Resources:
ECE 545: Lecture 11. Programmable Logic Memories. Recommended reading. Memory Types. Memory Types. Memory Types specific to Xilinx FPGAs
ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Resources: User
Migen. A Python toolbox for building complex digital hardware. Sébastien Bourdeauducq
Migen A Python toolbox for building complex digital hardware Sébastien Bourdeauducq 2013 FHDL Python as a meta-language for HDL Think of a generate statement on steroids Restricted to locally synchronous
Intel Quartus Prime Pro Edition User Guide
Intel Quartus Prime Pro Edition User Guide Design Compilation Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Design Compilation...
The Nios II Family of Configurable Soft-core Processors
The Nios II Family of Configurable Soft-core Processors James Ball August 16, 2005 2005 Altera Corporation Agenda Nios II Introduction Configuring your CPU FPGA vs. ASIC CPU Design Instruction Set Architecture
Spiral 2-8. Cell Layout
2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric
Atlys (Xilinx Spartan-6 LX45)
Boards & FPGA Systems and and Robotics how to use them 1 Atlys (Xilinx Spartan-6 LX45) Medium capacity Video in/out (both DVI) Audio AC97 codec 220 US$ (academic) Gbit Ethernet 128Mbyte DDR2 memory USB
Spiral 3-1. Hardware/Software Interfacing
3-1.1 Spiral 3-1 Hardware/Software Interfacing 3-1.2 Learning Outcomes I understand the PicoBlaze bus interface signals: PORT_ID, IN_PORT, OUT_PORT, WRITE_STROBE I understand how a memory map provides
Memory and Programmable Logic
Memory and Programmable Logic Memory units allow us to store and/or retrieve information Essentially look-up tables Good for storing data, not for function implementation Programmable logic device (PLD),
ECE 4514 Digital Design II. Spring Lecture 2: Hierarchical Design
ECE 4514 Digital Design II Spring 2007 Abstraction in Hardware Design Remember from last lecture that HDLs offer a textual description of a netlist. Through abstraction in the HDL, we can capture more
Using Library Modules in Verilog Designs. 1 Introduction. For Quartus II 13.0
Using Library Modules in Verilog Designs For Quartus II 13.0 1 Introduction This tutorial explains how Altera s library modules can be included in Verilog-based designs, which are implemented by using
VHDL in 1h. Martin Schöberl
VHDL in 1h Martin Schöberl VHDL /= C, Java, Think in hardware All constructs run concurrent Different from software programming Forget the simulation explanation VHDL is complex We use only a small subset
ECE 545 Lecture 12. FPGA Resources. George Mason University
ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks
Don t expect to be able to write and debug your code during the lab session.
EECS150 Spring 2002 Lab 4 Verilog Simulation Mapping UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 4 Verilog Simulation Mapping
Computer Structure. Unit 2: Memory and programmable devices
Computer Structure Unit 2: Memory and programmable devices Translated from Francisco Pérez García (fperez at us.es) by Mª Carmen Romero (mcromerot at us.es, Office G1.51, 954554324) Electronic Technology
FPGAs for Image Processing
FPGAs for Image Processing A DSL and program transformations Rob Stewart Greg Michaelson Idress Ibrahim Deepayan Bhowmik Andy Wallace Paulo Garcia Heriot-Watt University 10 May 2016 What I will say 1.
RECONFIGURABLE SPI DRIVER FOR MIPS SOFT-CORE PROCESSOR USING FPGA
RECONFIGURABLE SPI DRIVER FOR MIPS SOFT-CORE PROCESSOR USING FPGA 1 HESHAM ALOBAISI, 2 SAIM MOHAMMED, 3 MOHAMMAD AWEDH 1,2,3 Department of Electrical and Computer Engineering, King Abdulaziz University
Creating Computers from (almost) scratch using FPGAs, VHDL and FORTH. Recreative explorations of the hardware/software co-design space
Creating Computers from (almost) scratch using FPGAs, VHDL and FORTH Recreative explorations of the hardware/software co-design space Hans Hübner, ZSLUG Meetup, February 7th, 2011 Introduction Hacker since