TI C2000: Družina za vgrajene (embedded) aplikacije
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1 CPU MIPS RAM (words) ROM (words) Flash (words) BootROM (words) Event Manager CAP/QEP TIMER PM(CMP) ADC TIMER Resolution 12 # ofchan 16 Conv time McBSP EXMIF atch Dog SPI SCI (UART) CAN Volts (V) # I/O Package TI C2000: Družina za vgrajene (embedded) aplikacije bit F2812 F2808 bit LF2407A 16 bit LF2406A 16 bit LF2403A 16 bit LF2402A 16 bit LF2401A 16 bit LC2406A 16 bit LC2404A 16 bit LC2402A 16 bit LC2401A 16 bit 16 F243 bit 16 F241 bit F240 16bit 16bit C K 36K 2.5K 2.5K 1.0K 1.0K 1.0K 2.5K 1.5K K K 128K K K 16K 8K 8K 2K 2K K 6/6 4/2 6/4 6/4 3/2 3/2 1/0 6/4 6/4 3/2 1/0 3/2 3/2 4/2 3/ bit 12-bit 10 bit ns 160ns 500ns 500ns 500ns 500ns 500ns 375ns K 375ns 6K 425ns 8K 8K 500ns 900ns 1.8 core 1.8core I/O 3.3 I/O LQFP 128LQFP 144LQP00LQPF 64LQFP 64PQFP LQFP 100LQFP 179u*BGA 100LQFP 64PQFP 8K 900ns LQFP 144LQFP 64PQFP 68PLCC 16K 6.1us 4K 900ns 1PQFP 64PQFP 68PLCC 2-1
2 Povzetek visokozmogljivi -bit DSP x bit ali dvojni 16 x 16 bit MAC Atomski (atomic) ukazi za branja-spreminjanje-vpisovanje osemnivojski popolnoma zaščiteni cevovod Upravitelj (manager) za hitri odziv na prekinitev 128 Kw flash pomnilnik na čipu (on-chip) Code security module (CSM) Dva upravitelja dogodkov 12-bit ADC modul 56 deljenih (shared) digitalnih vhodno/izhodnih kanalov za splošne namene (GPIO) Časovnik za časovno stražo (atchdog timer) Komunikacijska periferija 2-2
3 Blokovna shema C2808 Program Bus Event Manager Event Manager A A(18-0) D(15-0) Realtime Realtime 22 Sectored Sectored Flash Flash -bit -bit Auxiliary Auxiliary x x bit bit Multiplier Multiplier Register Bus CPU RAM RAM R-M- R-M- Boot Boot ROM ROM PIE Interrupt Manager 3 bit bit Timers Timers Event Manager Event Manager B 12-bit 12-bit ADC ADC atchdog atchdog McBSP McBSP CAN2.0B CAN2.0B SCI-A SCI-A SCI-B SCI-B SPI SPI GPIO GPIO 2-3
4 -bit -bit x Auxiliary x bit bit Auxiliary Multiplier Multiplier Realtime Realtime Register Bus CPU C28x CPU Program Bus MCU/DSP uravnovešenost enost med gostoto kode in časom izvajanja: R-M- R-M- PIE Interrupt Manager 3 bit bit Timers Timers -bit DSP s fiksno vejico (fixed( fixed-point) x bit fixed-point MAC dvojni 16 x 16 fixed-point MAC (DMAC)( v enem ciklu -/64 /64-bitno zasičenje 64/ i / modulno deljenje podpira -bit bitne ukaze za izboljšanje časa izvajanja; podpira 16-bit bitne ukaze za izboljšano učinkovitost kode hitro servisiranje prekinitev (interrupts) ukazi za branje/spreminjanje/vpisovanje (read-modify-write)) v enem ciklu izredna sposobnost razhroščevanja (debugging)) v realnem času kompatibilnost kode navzgor 2-4
5 C28x množilnik (multiplier) in akumulator/enote za pomik( / Shifters) Program Bus XT () ali T/TL 16/ Shift R/L (0-16) 16 8/16/ MULTIPLIER x ali Dual 16 x 16 P () ali PH/PL Shift R/L (0-16) 8/16 AH (16) () ACC () AL (16) AH.MSB AH.LSB AL.MSB AL.LSB Shift R/L (0-16) 2-5
6 C28x kazalec podatkov (data pointer-dp) in pomnilnik Program Bus XAR0 XAR1 XAR2 XAR3 XAR4 XAR5 XAR6 XAR7 DP (16) MUX 22 MUX 6 LSB iz IR ARAU Data Memory XARn -bits ARn 16-bits 2-6
7 Struktura internih vodil C28x Program PC Decoder Program Address Bus (22) Program-read read () Data-read Address Bus () Program (4M* 16) Data-read () Data (4G * 16) ARAU SP XAR0 to XAR7 Execution MPYx XT P ACC R-M- Debug Real-Time Emulation & Test Engine Memory Standard Peripherals Register Bus / Result Bus Data/Program-write () Data-write Address Bus () External Interfaces 2-7
8 C28x Read/Modify/rite (beri/spremeni/vpiši) Prednosti: LOAD enostavnejše e programiranje CPU READ / MPY Mem krajša, a, hitrejša a koda brez prekinjanja STORE RITE učinkovitejši i (C) prevajalnik Standardno nalaganje /shranjevanje DINT MOV AND MOV EINT AL,*XAR2 AL,#1234h *XAR2,AL 6 besed / 6 ciklov Read/Modify/rite AND *XAR2,#1234h 2 besedi / 1 cikel 2-8
9 A B C D E F G H C28x cevovod (Pipeline) F1: naslov ukaza F2: vsebina ukaza D1: dekodiranje ukaza D2: ugotavljanje naslova operanda R1: naslov operanda R2: priskrbi operand X: CPU izvaja ukaz : rezultat shrani v pomnilnik F 2 D 1 D 2 R 1 R 2 RX 2 X R 1 Zaščiteni cevovod Osemnivojski cevovod F 2 D 1 D 2 R 1 R 21 RX 2 X D 2 Zaporedje rezultatov eneko tistemu iz izvirne kode Delovanje cevovoda ni skrb programerja E & G naslavljata enak naslov 2-9
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