DSP Processors Lecture 13

Transcription

1 DSP Processors Lecture 13 Ingrid Verbauwhede Department of Electrical Engineering University of California Los Angeles 1 References The origins: E.A. Lee, Programmable DSP Processors, Part I, IEEE ASSP magazine, October 1988, pg Part II, IEEE ASSP magazine, January 1989, pg Good overview: P. Lapsley, J. Bier, A. Shoham, E.A.Lee, DSP Processor Fundamentals: Architectures and Features, IEEE Press, More references: P. Faraboschi, G. Desoli, J. Fisher, The latest word in Digital and Media Processing, IEEE Signal Processing Magazine, March 1998, pg , (download from the INSPEC webpage). I. Verbauwhede, M. Touriguian, Wireless Digital Signal Processors, Chapter 11 in Digital Signal Processing for Multimedia Systems, Eds. By K. Parhi, T. Nishitani, Marcel Dekker, Inc. C. Nicol, I. Verbauwhede, DSP Architectures for Next Generation wireless communications, ISSCC 2000 tutorial. 2 1

2 Recall: architecture FIR execution on: Von Neumann: 3 cycles/tap Basic Harvard: 2 cycles/tap Modified Harvard & repeat loop: 1 cycle per tap & only 3 instructions Key issues: bandwidth by multiple memory banks or multi port memories Every memory has its OWN address generation unit operating in parallel Special instructions that combine operations with memory moves: MACD Indirect addressing: *r1++ or *r2-- circular buffers: extra hardware in the address generation units FASTER THAN 1 CYCLE PER TAP?? 3 Compute Intensive function 1: FIR (cont.) y(n) = N-1 c(i) x(n-i) Σ i=0 x(n) c(0) X x(n-1) Z -1 Z -1 Z -1 (50 TAPS) X X c(n-1) X x(n-(n-1)) y(n) y(0) = c(0)x(0) + c(1)x(-1) + c(2)x(-2) c(n-1)x(1-n); y(1) = c(0)x(1) + c(1)x(0) + c(2)x(-1) c(n-1)x(2-n); y(2) = c(0)x(2) + c(1)x(1) + c(2)x(0) c(n-1)x(3-n);... y(n) = c(0)x(n) + c(1)x(n-1) + c(2)x(n-2)+.. + c(n-1)x(n-(n-1)); One output = 2N reads, N MAC s, 1 write Classic Harvard: one output = N cycles 4 2

3 FIR speed-up FIR filtering: two outputs in parallel y(0) = c(0)x(0) + c(1)x(-1) + c(2)x(-2) c(n-1)x(1-n); y(1) = c(0)x(1) + c(1)x(0) + c(2)x(-1) c(n-1)x(2-n); y(2) = c(0)x(2) + c(1)x(1) + c(2)x(0) c(n-1)x(3-n);... y(n) = c(0)x(n) + c(1)x(n-1) + c(2)x(n-2)+.. + c(n-1)x(n-(n-1)); Two outputs = 4N reads, 2N MAC s, 2 writes Dual Mac Architecture with ONLY 2 data busses?? Read two -bit numbers instead of four -bit numbers Solution by Lucent 000 core with dual MAC Run MAC at double frequency, read two -bit numbers Solution by Matsushita Insert delay register Solution by Atmel s LODE 5 Example 3: Lucent DSP210 Inner loop of -tap FIR Filter do 14 { //one instruction! a0=a0+p0+p1 p0=xh*yh p1=xl*yl y=*r0++ x=*pt0++ } Outer Loop: 19 cycles, 38 bytes 1 cycle in inner loop 5 exec units used in inner loop 2 MACs per cycle Y() x mpy x mpy p0 () p1 () Shift/Sat. X() Shift/Sat. XDB() IDB() Horizontal parallelism, one sample at a time ADD BMU 2G mobile wireless base-stations ACC File 8 x 40 Courtesy: Gareth Hughes, Bell Labs Australia 6 3

4 FIR on Lode FIR filter: two outputs in parallel with delay register y(0) = c(0)x(0) + c(1)x(-1) + c(2)x(-2) c(n-1)x(1-n); y(1) = c(0)x(1) + c(1)x(0) + c(2)x(-1) c(n-1)x(2-n); y(2) = c(0)x(2) + c(1)x(1) + c(2)x(0) c(n-1)x(3-n);... y(n) = c(0)x(n) + c(1)x(n-1) + c(2)x(n-2)+.. + c(n-1)x(n-(n-1)); Total energy for one output sample: Energy Single MAC Dual MAC Dual MAC with REG No. of MAC operations N N N No of reads 2N 2N N No of Instruction Cycles N N/2 N/2 7 FIR on Lode Two MAC units with dedicated bus network DB1() DB0() DB0 fetches coefficient c(i) x(n-i+1) LREG x(n-i) c(i) DB1 fetches data LREG delays input data A0 stores y(n) output A1 stores y(n+1) output MAC1 X + X + MAC0 y(n+1) A0 y(n) A1 Same structure can be used for IIR 8 4

5 Arithmetic DSP processors come in two flavors: floating point most popular one: Sharc s from Analog Devices fixed point usually bit, sometimes 24 bit (audio processors) newer processors might have wider data paths or registers (TI C6x: x mpy, bit registers, ) Basic datapath bit x mpy shifter Select bit 9 Overflow: Saturation logic combined with output shifter bit x mpy Shifter/ saturate Select bit How to implement saturation? 10 5

6 Overflow: Input shifter: scaling, line up of the inputs = loss of precision if shift to much down. x mpy input Shifter bit Shifter/ saturate Select bit 11 Block normalization Often used in speech coders because dynamic range of the input signals is unknown. Scale the whole array of values such that the maximum entry sits in the range [0.5, 1) minimum loss of precision TIC54x: EXP A NORM A <- counts number of sign bits, stores this number in TREG <- shifts the accumulator by the number of bits in TREG Lode: Repeat N; A3 = expmn (*r0), r0++; (stores # of sign bits in special register ASR) Repeat N; *r0 = *r0 < ASR, r0++; 12 6

7 Pipelining: Time = fetch instruction = decode instruction access = address generation and read operands = perform operation 13 Pipelining How does pipeline appears to the programmer? Lee s paper (part II) discusses 3 variations (the difference is often blurry): interlocking time stationary coding data stationary coding Interlocking: the instructions appear if executed one after another 14 7

8 Interlocking on C10 LT LTD Reservation table: PMEM LT LTD LTD DMEM data coef1 data coef Interlocking on C2x Programmer does not know the pipeline If an access conflict occurs: hardware will stall and finish one (part) of an Instruction before finishing a second part. RPTK 49 MACD Reservation table: PMEM RPTK MACD coef1 coef2 coef3 DMEM data1 data2... 8

9 Single Cycle MAC TMS0C2x Multiplier/ Program Bus Data Bus Left T Register () MUX Shifter (0-) Multiplier (x) P Register () Left Shifter (0-) MUX Arithmetic Logic Unit () C Accumulator Register () Left Shifter (0-7) Single Cycle x bit Multiply yielding a -bit product Supports simultaneous Program and two Data Operand acquisition Supports simultaneous and Multiplier operations 0- bit Left Post-Shifter Courtesy: Texas Instruments 17 Example: MACD MACD = Multiply by Program and Accumulate with Delay (Instruction is still present in C54x and C55x) MACD Smem, pmad, src Smem = data memory pmad = program address src = accumulator (A or B) s (simplified): (Smem) x (Pmem(at location pmad)) + src -> src ; = multiply accumulate (Smem) -> Treg ; load data in Treg register (Smem) -> Smem +1 ; load data in next mem loc. (pmad) +1 -> pmad ; increment program address pointer When executing with a repeat instruction, takes one cycle 18 9

10 Time stationary Instruction specifies one instruction cycle. So it specifies, all that occurs in parallel. Example: Motorola: MAC X0, Y0, A X:(R0)+, X0 Y:(R4-), Y0 (multiply-acc of values read from memory in the previous cycle Lucent x a0 = a0 + p, p = x * y, y = *r0++, x = *pt Data stationary Time stationary: working on different samples in one instruction Data stationary: describes what happens with one input data from start to end. Example (Lode): *r3++ = a0+ = a2 * *r2++; (read from memory with pointer reg r2, Multiply with a2, add to a0 and store back in a0, Store the result in memory with pointer r3, Post modify r2 and r3) Read Write 20 10

11 Control & Pipeline for DSP s RISC: load/store machine memory access with load/store instructions (DLX, MIPS, D10V) Write Back access / branch Execution/ address generation Excellent for complex decision making! DSP: register-memory architecture (TI, Lucent, HX, Lode) Write Back Execution access Excellent for number crunching! 21 Pipeline RISC compared to DSP RISC:example r0 = *p0; // load data a0 = a0 + r0; // execute Too expensive for DSP DSP: memory intensive applications: Penalty: data dependent branch is expensive 22 11