Next Generation Microprocessor for Power Systems Control September 2006 M. Ruiz, SABCA, Belgium

Size: px

Start display at page:

Download "Next Generation Microprocessor for Power Systems Control September 2006 M. Ruiz, SABCA, Belgium"

Gyles Copeland
6 years ago
Views:

1 Next Generation Microprocessor for Power Systems Control September 2006 M. Ruiz, SABCA, Belgium 1

2 Next Generation Microprocessor for Power Systems Control Presentation Overview Scope Microprocessor architecture overview SW development tools Next generation architecture 2

3 Scope Power systems control is rapidly evolving: Control algorithms become more and more complex Reliability, weight and cost become more and more critical Community, pushed by high progress made in microelectronics, needed a cheap, hard real-time and safe microprocessor The microprocessor is called BRISC to refer to its architecture: Bi: Risc: µp holds a dual floating-point unit RISC architecture Design started in the 90 s at Université Catholique de Louvain, Belgium Latest release, HBRISC2, is the radiation-hardened release of BRISC (developed in the scope of a GSTP2 program, in collaboration with ESA- ESTEC) 3

4 BRISC Architecture Overview GSTP2-IMCM goal: Develop and qualify a generic platform allowing control of a wide range of motor and drive electronics for space mechanisms The core of the platform is the HBRISC2 microprocessor Platform provides A customized library, allowing development & simulation within Simulink environment An automatic binary code generation function, thus decreasing software design effort A user-friendly environment for application debugging/fine-tuning/validation 4

5 BRISC Architecture Overview Microprocessor Key Features: Versatile, standard product RISC machine, uninterruptible: Fully predictable execution time Easier SW validation Saturating floating-point data format (16-bit mantissa, 8-bit exponent) Power systems data require high dynamic Rescaling, overflow study,... is avoided Full application data visibility, at Simulink-level Easier SW validation 5

6 BRISC Architecture Overview Microprocessor Key Features: Fast on-chip memory data Avoid access to (slow) external RAM Automatic SEU correction (EDAC) of internal and external RAM upsets Fully transparent for application SW 1-bit errors are detected AND corrected N-bit erros are detected and reported Built-in autonomous and configurable functions required for power system control (PWM, sensors excitation, ADC interface,high-speed reporting ) Decreases CPU load 6

7 BRISC Architecture Overview: Functional Diagram Program bus INSTRUCTION REGISTER 32+7 HBRISC2 CORE 16 ADDRESS REGISTER Address bus HBRISC2 ON-CHIP SEU ERROR DETECTION/ CORRECTION Unit A GLOBAL REGISTERS REGISTER BANK FLOATING POINT UNIT INSTRUCTION DECODER Unit B GLOBAL REGISTERS REGISTER BANK FLOATING POINT UNIT ON-CHIP MEMORY SEU ERROR CORRECTION UNIT GLOBAL REGISTERS FIXED POINT ARITHMETIC UNIT RIO Unit SU RPAD INSTRUCTION SEQUENCER BOOT ROM REGISTERS SEU DETECTION/ CORRECTION UNIT 46 / ADC interface I/O interface ON-CHIP PERIPHERAL INTERFACE Peripheral bus Prog. outputs Serial port (SPI) 4 / 3 / / 1 CRC check motor PWM excitation PWM Serial Fast link software timer HBRISC2 PERIPHERAL

8 BRISC Architecture Overview: HBRISC2 ASIC Technology ATMEL MH1RT y y y y y y Rad-Tolerant Latch-up immune SEU hardened registers Gate-array 0.35 µm 5V I/O pads 3.3 V Core HBRISC2 y Matrix: MH1_156E y Package: MQFP-256 y 4 on-chip dual-port RAM Bank registers SPI interface buffers Performance: y 60 MFLOPS y 30 MIPS 8

9 BRISC Architecture Overview : SW development tools SIMULINK library (lib_imcm.mdl) Macro definition (macros.lst) Macro library (bh files) Target hardware SIMULINK model Simplified (mdl file) Synthesised SIMULINK model (mdl file) SYNTHESISER Code source (b2c file) Compilation Hbrass2.exe Binary code (bin file) Software validation testing (Seracq-Win32) Variable definition file (m files) HBrisc2 parameter initialisation (initialisations.bc) Generated Code Key Features: Macro-based Static register allocation OS-free Fully static and sequential execution 9

10 BRISC Architecture Overview: Applications Mainly Motor-Control applications Space: TVC (Thrust Vector Control) for the 4 stages of the VEGA Launcher (SABCA, Belgium) Tip-Tilt Mechanism: mirror fine-pointing application (GSTP3, CSEM, Switzerland) Military/Civil Aerospace: License sold to Dassault Electronique for M51 Several demonstrators developped for A320 primary flight control F-16 pod air-conditionning: sensorless control 10

11 Towards Next BRISC Generation Non-intrusive background interface for SW validation Facts: Validation can not be (safely) performed with instrumentation code Validation must be made at processor full-speed The processor can not be interrupted Need for standardized non-intrusive interface: Nexus? ASIC technology: Allow a higher integration of peripherals: RAM, EEPROM, ADC, IP,... Need for new ASIC technology sources: SOI (Silicon-On-Insulator): preliminary meetings are encouraging Other? 11

12 Towards Next BRISC Generation Towards IP availability Easy integration into an FPGA, ASIC, SoC,... Configurable architecture to better suit target application Standardized SW tools C compiler Simulink tool-box IEEE floating data format Simulator Automatic generation of the initialisation file 12

GSTP2-IMCM. Final Presentation December 2004

GSTP2-IMCM. Final Presentation December 2004 GSTP2-IMCM ESTEC/Contract N 13492/99/NL/PA Final Presentation December 2004 1 IMCM Project Assessment BRISC architecture Targeted applications Architecture overview IMCM ASIC HBRISC2 development logic