Dr. Ishaq Unwala Rockwell Pl Phone #: (512)

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1 Dr. Ishaq Unwala Rockwell Pl Phone #: (512) Austin, TX WORK EXPERIENCE University of Houston Clear Lake, Houston, TX Aug '14 - present Assistant Professor of Computer Teaching graduate level classes in Computer. Areas of interest Design, Test and Verification of digital designs. Oracle Corporation, Austin, TX Senior Hardware Engineer Sep '10 - Jan '14 Recently employed at Oracle Corporation in Computer and Microelectronic Technology (CMT) division, formerly Sun Microsystems. The CMT division designs, develops and implements complete SPARC systems, including SPARC Core, SOC for SPARC Core, and Solaris Operating System. I was responsible for functional verification of the SPARC Core. I have worked on two SPARC processor cores, Tahoe (S4) and Siete (S5). Functional verification includes many sub-tasks, including working with logic design team on design specification documents, Test Generation, Test Environment design and development, Functional Coverage specification and implementation, root causing Test failures, Formal verification, use and design of many other Design Tools. - Project : Siete (S5) CPU ( ) Most recently I worked on design verification of the Load Store Unit for a new SPARC processor. I proposed, specified, and implemented a new test generator for testing of the Load Store unit (LSU) for the SPARC Core. The new test generator provided hundreds of tests that otherwise would have to be hand written. I wrote testing and coverage specification for LSU blocks. Design and verification work is still in progress. Siete is projected to tape-out in March Project : Tahoe (S4) CPU ( ) I specified, designed and implemented the unit test environment (UTE) for the Instruction Fetch Unit (IFU) design for Tahoe. UTE was used to perform detailed verification of various IFU hardware structures, including the instruction cache, instruction TLB, hardware instruction fetching and prefetching, multiple branch predictors and branch information tables. UTE consisted of behavioral, emulation, irritator, monitor and checker modules written in Synopsys Vera. UTE also modeled pseudo random stimulus and response of peripherally units. UTE also generated pseudo random and directed pseudo random configuration. Using behavioral code UTE modeled all the internal units to generate expected results for functional checking. Intrinsity Inc, Austin, TX Member Technical Staff Apr '08 - Aug '10 Intrinsity was a small CPU design and development company that was bought by Apple, Inc. in Intrinsity worked on design and development of PowerPC and ARM cores. At Intrinsity, original RTL was redesign to improve its clock speed and performance. To prove that the re-design RTL was functionally same as the original RTL we used Formal commercial tools. The formal tools included, Sequential Equivalence Checker (SLEC), Conformal and Solidify. - Project : Dual Core ARM Cortex-A9 CPU ( )

2 I performed formal validation on a dual core ARM Cortex-A9 processor implementation. The formal validation methodology mainly used SLEC with an occasional use of Solidify and Conformal to prove certain cases. The CPU was used delivered to Samsung for use in the Samsung Galaxy II cellphone and the Samsung Galaxy tablet. - Project : ARM Cortex-A8 CPU ( ) I performed formal validation on an ARM Cortex-A8 processor implementation. This processor was released in 2009 as Hummingbird by Intrinsity/Samsung. Hummingbird won the IEEE Spectrum Mobile CPU award for 2009, "Intrinsity's More Cerebral Cortex", in the January 2010 issue. Hummingbird was also featured in the Microprocessor Report of July 2009, "Hot-Rodding the Cortex-A8". The formal methodology mainly used SLEC, with occasional use of Conformal and Solidify tools. Hummingbird was used in Apple ipad-1, Apple iphone4, and Samsung Galaxy-S cellphone. Intel Corporation, Austin, TX Senior Microarchitecture Validation Sep '00 - Apr '08 Intel is one of the largest semiconductor companies in the world. Intel designs, develops and manufactures a wide range of semiconductor products, most of which use Intel x86 architecture based microprocessors. Intel x86 microprocessors are used in a wide range of applications, including embedded applications, cell phones, tablets, laptop, desktop, and servers. At Intel I worked on multiple projects. - Project : Bonnell (Intel ATOM) CPU ( ) Bonnell was a low power microarchitecture design initiative by Intel for the mobile devices market. I performed verification on both unit level and core level. I designed, developed and implemented the Front- end module's (FEC) unit test environment (UTE). FEC design consisted of instruction fetch, decode, Icache, TLB, multiple branch predictors, microcode (µ-code) related functions like µ-code sequencing and µ-code patching. FEC UTE consisted of behavioral, irritators, emulations, monitor, and checker modules for each of the design structures. After unit level work, I joined Bonnell core level verification in the final year of the project. Verification tasks consisted of UTE support, test writing, debugging and determining the fails, specifying, implementing and achieving functional coverage goals. I also worked on silicon bring up and initial postsilicon validation. The Bonnell processor was used in netbooks and latest version is used in mobile phones and tablets. - Project : Merom (Intel CORE2) CPU ( ) Verified advance performance enhancement features on Merom microprocessor using functional coverage, random test generation and debugging fails. Merom was released as Intel CORE2 for laptop market. - Project : Tejas CPU ( ) Tejas CPU was a high performance, high frequency Pentium4 design. I designed, developed and implemented FEC UTE for unit level verification. The FEC design consisted of instruction fetch, decode, Icache, TLB, multiple branch predictors, microcode (µ-code) trace cache, µ-code sequencing and µ-code patching. I worked on verification of full Tejas core during the last two years of the project. Developed specialized C++ based checkers and irritators to verify various design structures. I also worked on verification of the Sequencer and Rename Replay Queue units. Verification

3 tasks consisted of UTE support, test writing, debugging and root causing the fails, specifying, implementing and achieving functional coverage goals. IBM Corporation, Austin, TX Advisory Engineer Jun '98 - Sep '00 IBM is one of the largest and the most respected companies in the world. IBM was developing the first processor with gigahertz clock speed when I joined the company. - Project : Power4 CPU ( ) I worked at IBM on the Gigahertz Processor (GP/Power4). Responsibilities at IBM included definition and implementation of microarchitecture coverage models in consultation with design team for GP project using COMET (COverage METric). Analysis of test coverage and reporting of coverage holes to the verification team. I guided GP microarchitecture coverage project from the tools and resource requirement perspective. I also worked with verification tools team to improve the coverage tools and flow. VLSI Technology Inc, Tempe, AZ Senior software design engineer Jun '95 - May '98 VLSI Technology was a small semiconductor and EDA company. VLSI Technology was bought by Phillips Semiconductor. I defined, designed, and implemented Electronic Design Automation (EDA) tools for Application Specific Integrated Circuit (ASIC) design flows. I developed analysis tools for gate-level designs specified in Verilog, VHDL and EDIF, specifically VLSI Netlist Screener and VLSI Delay Calculator Command Shell. I supervised development of a number of support tools for internal use within VLSI Technology, Inc. - Project : VLSI Netlist Screener ( ) I defined, developed, implemented and maintained the design netlist screening tool. The tool's main function was to do Design Rule Check (DRC) for electrical correctness and standard cell library rules compliance. - Project : VLSI Delay Calculator Command Shell ( ) I defined, developed, implemented and maintained the Delay Calculator Command Shell tool. The tool was an integration effort to allow our customers interactive queries on the delay calculator database after the delay calculation was completed. The University of Texas at Austin, Austin, TX Graduate Research Assistant Jan '92 - May '95 Conducted research on various aspects of computer architecture and developed modeling software for resulting techniques. Topics included pipelined processor modeling and design evaluation, superpipelined processor design, and instruction set architecture. Issues such as dependencies, execution interlocks, branch target fetch delays and instruction sequences were investigated. Computer Services Company Pakistan Hardware and Software Consultant Mar '86 - Dec '91 Owned and operated Computer Services Co. Provided expertise and counsel on hardware purchases, upgrades and maintenance service to medium sized companies. Designed integrated software systems for accounting, sales and MIS.

4 EDUCATION Doctor of Philosophy (Computer ) May '98 The University of Texas at Austin, Austin TX Department of Electrical and Computer Master of Science (Computer ) May '86 The University of Texas at Austin, Austin TX Department of Electrical and Computer Bachelor of Science (Electrical ) May '84 West Virginia University, Morgantown, WV Department of Electrical and Computer PH. D. DISSERTATION "Markov Chain Modeling and Design Evaluation of Pipelined Processors" Developed pipelined processor modeling and design evaluation technique based on Markov chains. Implemented an instruction trace-driven pipeline simulator based on these models. Established that the Markov chain model is a good approximation for a processor pipeline. M.S. THESIS "A Novel Environment for Design and Simulation of Digital Systems Architecture" Designed and simulated architecture for a floating-slash math-coprocessor. The inspiration for design of math co-processor came from floating-slash arithmetic ideas of Dr. David W. Matula at Southern Methodist University, Dallas. The math-coprocessor was simulated using Lotus 123 spreadsheet. Lotus 123, and other spreadsheet programs, have a built in macro language to write code. The language includes ability to model clocking, logic equations, and cell based state machines. Using these capabilities I simulated microcode, assembly language and hardware for the math-coprocessor using Lotus 123 software. PUBLICATIONS Ishaq H. Unwala and Harvey G. Cragon, "A Markov Chain Modeling Technique for Evaluating Pipelined Processor Designs," IEEE 37th Midwest Symposium on Circuits and Systems, pp , vol. 1, August 1994, Lafayette, LA. Ishaq H. Unwala and Harvey G. Cragon, "Design Evaluation of Pipelined Processors Using Finite State Machine Analysis with Markov Chains," 3rd International Conference on the Economics of Design, Test and Manufacturing, pp May 1994, Austin, TX. Ishaq H. Unwala and Earl E. Swartzlander, Jr., "Superpipelined Adder Designs," 1993 IEEE International Symposium on Circuits and Systems, pp , May 1993, Chicago, IL.

5 Ishaq H. Unwala and Harvey G. Cragon. "A Study of MIPS Programs," Computer Architecture News, vol. 22, no. 5, December 1994, pp TEACHING The University of Houston Clear Lake, Houston, TX Assistant Professor of Computer Teaching graduate courses in area of Computer. Aug 2014-present The University of Texas at Austin, Austin, TX Adjunct Faculty position Jan '01 In 2001, I had the privilege and an opportunity to teach an upper division undergraduate Computer Architecture class in the Computer Science Department at the University of Texas at Austin. While working at Intel Corp, I accepted the position of Adjunct Faculty and taught the undergraduate Computer Architecture class for one semester. RESEARCH INTERESTS Computer architecture and micro-architecture Digital systems design Hardware design verification techniques and technologies Formal verification methods Functional coverage Simulation techniques CAD tools, technologies and techniques