Efficient Systems. Micrel lab, DEIS, University of Bologna. Advisor

Transcription

1 Row-based Design Methodologies To Compensate Variability For Energy- Efficient Systems Micrel lab, DEIS, University of Bologna Mohammad Reza Kakoee PhD Student it Luca Benini Advisor

2 Introduction Motivation of the work How to Compensate the circuit slow down in presence of process variation The compensation procedure should have as less as possible power overhead Contribution Speed-up the slow designs using Forward Body Bias (FBB) Speed-up the slow designs at near-threshold using Dual-Vdd Novelty Unlike other methodologies, we do NOT speed-up the entire block or chip but just Timing critical gates We incur very low leakage power overhead

3 Row-based compensation Layout rows as atomic candidate blocks for FBB or Multi-Vdd. Some rows are on critical paths and others not. They could be divided in different clusters and be treated differently. In case of variation, only critical rows need to be boosted.

4 Row-based Speed-upp Critical Rows Critical row Cells Speed-up Critical Row Critical Row Timing Check Layout

5 Designing in Near Threshold Region Designs that can make use of sub threshold operation have been shown in the literature. FFT processor [A. Chandrakasan.ISSCC 04], Sensor application processor [D.Blaauw.TVLSI 09] Near threshold operation is more robust as compared to sub threshold MEP operation [Rabaey.IEEE 10] Higher Static Noise Margin Higher functional yield Less Delay and Leakage Power Variability Offers much higher performance and hence suited for wide range of applications Should sacrifice 2 3X power Challenges to be addressed Delay and leakage power variability still higher as compared to superthreshold operation 5

6 Row Based ddual Vdd Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini: Automatic synthesis of near-threshold circuits with fine-grained Performance Tunability, ISLPED 2010: Post silicon tuning techniques can help to mitigate performance and leakage variability At near threshold regime, small changes in supply voltage results in drastic changes in performance and power Row based dual vdd can yield good speed up with very low power overhead Level shifter less fine grained ddual vdd Since the two supply voltages are very close to each other, no level lshifters are used between different voltage domains 6

7 Dual-Vdd Row Assignment VDDL Row-based standard GND cell design VDDH Row VDDH VDDL VddH row GND Partition rows into two sub-sets: VddH set and VddL set Overall timing for desired speed-up is met VddL Set VDDL Minimizing power VDDH overhead VDDH Row VddH GND row VddH Set Row separation is needed if two adjacent rows share one Vdd VDDL VDDH Row VDDH VddH row GND Power Rows Row Separation Cells

8 Dual-vdd post silicon tuning Vdd1 VddL Vdd2 Switch VddH Dual-Vdd Design Compensate? 8

9 Dual-vdd row assignment Heuristic Algorithm Sort rows in Descending order based on TFactor done Two-phase greedy algorithm Phase 1 Foreach Row r TFactor(r)=0; Foreach Timing Path P Count=0; Phase N most 1: Prioritizing critical paths rows based on timing (N is set by designer) criticality factor done Foreach Cell c in r done TFactor(r)=TFactor(r)+Count*Delay(P); () () ); Timing Criticality Factor c exist in P? Yes Count++; No

10 Heuristic Algorithm Phase 2 2 Sorted Rows Phase 2: Computation Assign Cost= the Max( most Phase1,Phase2) critical rows to Get the next critical Row r VddH until the O(Phase1) desired = O(CP*R*C) speed-up is met CP: number of timing critical paths R: number of Rows Select the next C: maximum number VddH if of speed- cells in a row up is not met O(Phase2)= O(R) done Assign r to VddH Computation Cost = O(CP*R*C) Linear in the number or rows Linear in the number of critical paths Yes Stop Speed-up is met? No

11 Experimental Setup 90nm TSMC library (SVT, 0.2 Vth) is characterized for [0.4V, 0.45, 0.50,0.55,0.6,0.65, 0.7V] with ETS 8b benchmarks are physically placed using SoCEnc Heuristic algorithm is implemented in PrimeTime Spice Simulation is done to calculate the interface leakage for all cells and for each pair of (VddL, VddH). D l Vdd P i d ith th t f Si l Dual-Vdd s Power is compared with that of Single - Vdd approach for different speed-up factors

12 Experimental Results Power of Single Vdd 45% speed-up if using 0.45V instead of 0.4v VddH=0.45V VddH=0.50V Power consumption of DualVdd depends on speed-up factor Here DualVdd s power is more than SingleVdd due to interface gates

13 Experimental Results Cont d Layout of Simple ALU with DualVDD Row Separation is not needed in this Layout Spice Simulation of simple ALU after DualVdd assignment Even for such a small design our Dual-Vdd approach shows better SPICE results. However, dual-vdd is best suited for large designs with many number of rows and timing paths. Power (uw) Power_0.4_0.45 Power_0.45 Spice simulation on alu 5.00% 10.00% 20.00% 30.00% 40.00% Speed-up SingleVdd with Vdd=0.45V DualVdd with VddH=0.45V and VddL=0.40V

14 Forward Body Bias (FBB) FBB is a well-known approach to speed-up designs in case of variation FBB is applying forward body bias to decrease the threshold voltages of the devices It has high leakage overhead It is not needed to speed-up all cells

15 FBB Leakage overhead in chain of inverters % % leakage e overhea ad % 32nm % 45nm % % 00% % % 00% 65nm % 50.00% 00% 0.00% 0.00% 5.00% 10.00% 15.00% 20.00% 25.00% speed-up

16 Row-based FBB allocation Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini: i Fine-grained i Post Placement FBB for Variability Compensation in Nanometer CMOS design, Submitted to IEEE TVLSI. Pass One Assign all Rows to FBB Min Check Timing YES return FBB opt NO Assign all Rows to higher FBB Go to step 2 Pass Two (Heuristic) All Rows assign to FBB opt Perform Row Ranking based on their timing criticality Drop least critical row to FBB Lower Check Timing YES go to step 3 NO Fix the row back to FBB Higher Do steps 3-5 till C clusters formed Try other rows for lower FBBs in the clusters

17 FBB placement flow Novel physical layout design Support very fine grained tuning Low routing and area overhead Compensation o is done at row level granularity Layout style allows access to each row for applying FBB

18 Experimental Setup We apply our algorithm on a set of industrial designs including: ARM926EJS processor from ARM, LEON3 processor from Gaisler, 12x12 NoC switch from inocs, 32- bit Multiplier 3 FBB libraries at 32nm provided by ARM 150mv, 300mv, 450mv We also performed experiments using ST 45nm We characterized libraries using Cadence ETS Comparing results for three different cases Base design without any FBB Normal FBB with all rows assigned to the same FBB lib to obtain desired speed-up (after pass 1 of our algorithm) Our algorithm for FBB allocation (after pass 2)

19 Results in 45nm

20 Conclusion Variations are becoming a big challenge Post silicon tuning is needed to compensate the effect of variability on performance FBB and Multi-Vdd are two well-known techniques to increase the performance of designs New methodologies are needed to minimize the power overhead of these approaches We proposed row-bases techniques to selectively speed-up the critical rows Large improvements in leakage power reduction compared to existing post fabrication tuning techniques

21 Ongoing Work The current row-based algorithms are postplacement They can be improved if they are integrated into the placement phase Performing the placement in such a way that critical cells are placed near each other and din a few rows

22 Thank you for your attention. Any Question?