Near-Threshold Computing: Reclaiming Moore s Law

Transcription

1 1 Near-Threshold Computing: Reclaiming Moore s Law Dr. Ronald G. Dreslinski Research Fellow Ann Arbor 1 1

2 Motivation Transistors (100,000's) Power (W) Performance (GOPS) Efficiency (GOPS/W) Limits on heat extrac6on 1 Stagnates performance growth Limits on energy- efficiency of opera6ons

3 Motivation Transistors (100,000's) Result: Con6nue scaling trends that fueled the compu6ng revolu6on Power (W) Performance (GOPS) Efficiency (GOPS/W) 1000 With the help of some beber thermal management Goal: To increase energy- efficiency of operagons Era of High Performance Compu6ng Era of Energy- Efficient Compu6ng c

4 Outline 4 Define a new region of operation, Near-Threshold Computing Explore new architectures enabled by key insights of computing in the NTC region Present an initial design of a 3D stacked NTC system, Centip3De 4 4

5 Power Density Limitations Circuit supply voltages are no longer scaling 5 Power does not decrease at the same rate that transistor count increases Form factor vs. Battery Life Environmental Concerns Stagnant Shrinking Dynamic dominates A = gate area scaling 1/s2 C = capacitance scaling < 1/s Dark Silicon The emerging dilemma: More and more gates can fit on a die, but not all can be turned on at the same time 5 5

6 Today: Super-Vth, High Performance, Power Constrained 6 Energy / Operation Super-Vth 3+ GHz 0.5 mw/mhz Log (Delay) Normalized Power, Energy, & Performance Energy per operation is the key metric for efficiency. Goal: same performance, low energy per operation 0 Vth Vnom Supply Voltage Core i7 6 6

7 Sub-Vth 0 7 Super-Vth 12-16X Log (Delay) Energy / Operation Subthreshold Design X Operating in the sub-threshold gives us huge power gains at the expense of performance OK for sensors! Vth Vnom Supply Voltage 7 7

8 Evolution of Subthreshold Designs 8 Subliminal 1 Design (2006) µm CMOS -Used to investigate existence of Vmin µw/mhz Phoneix 1 Design (2008) µm CMOS -Used to investigate sleep current -2.8 µw/mhz / 30pW sleep power Subliminal 2 Design (2007) µm CMOS -Used to investigate process variation -3.5 µw/mhz Phoenix 2 Design (2010) µm CMOS -Commercial ARM M3 Core -Used to investigate: Energy harvesting Power management µw/mhz 8 8

9 Sub-Vth 9 Super-Vth ~6-8X ~2X Log (Delay) Energy / Operation Near-Threshold Computing (NTC) Near-Threshold Computing (NTC): >60X power reduction 6-8X energy reduction Invest portion of extra transistors from scaling to overcome barriers ~50-100X ~10X 0 Vth Vnom Supply Voltage 9 9

10 Silicon Verification of Trends 10 Phoenix 2 Processor Phoenix 2 Design [Seok 11] 180nm Design 1.8V -> 700mV ~10x NTC Performance Loss ~7x NTC Energy Reduction Seok ISSCC

11 NTC Opportunities and Challenges Opportunities: New architectures Optimized Processes 3D Integration less thermal restrictions Challenges: Low Voltage Memory New SRAM designs Robustness analysis at near-threshold 11 Variation Razor [Ernst 03] and other in-situ delay monitoring Adaptive body biasing Performance Loss Many-core designs to improve parallelism Core boosting to improve single thread performance 11 11

12 Outline 12 Define a new region of operation, Near-Threshold Computing Explore new architectures enabled by key insights of computing in the NTC region Present an initial design of a 3D stacked NTC system, Centip3De 12 12

13 Minimum Energy SRAM 13 Total Dynamic Leakage SRAM has a lower activity rate than logic VDD for minimum energy operation (VMIN) is higher Running logic at VMIN for SRAM has a small energy penalty with increased performance 13 13

14 New NTC Architectures 14 Next Level Memory Next Level Memory BUS / Switched Network BUS / Switched Network L1 L1 L1 L1 L1 Core Core Core Core Core Cluster Cluster L1 Key Insight: Cluster Cluster Core L1 L1L1 Core Core L1 Core SRAM is run at a higher VDD than cores with little energy penalty, allowing caches to operate faster than the core Design Levers: Operating Voltage L1 Size Number of Cores per Cluster Number of Clusters 14 14

15 L1 Cache Size Tradeoff Core 15 Core Decreased Miss Rate L1 Higher Energy/Access L2 L1 L

16 Results Energy Optimal L1 Size (Single Core) 16 Energy dependency on L1 size Trade-off between L1 and L2 access 16 16

17 Clustering Tradeoffs CPU CPU CPU CPU L1 L1 L1 L1 O L2 X 17 CPU CPU CPU L1 X Tradeoffs Clustered Sharing - Cluster Conflict - New Bus - L1 Speed CPU L1 L

18 Energy Optimal Cluster-based CMP (Fixed Die Size)

19 Full Space Analysis

20 Various Scaling Methods Normalized Energy/Operation 1 4 Cores 4 L1 s % L1 Core Simple CMP One core per L1 Vdd scaling Proposed clusterbased CMP Multiple cores per L1 Vdd scaling 53% 2 Cores/Cluster 3 Clusters Uniprocessor CMP w/ DVFS Baseline Single 233MHz L2 38% NTC 20 20

21 Energy Optima for SPLASH2 21 Cluster based architecture with Vdd and Vth scaling Optimal cluster size is 2 for most of the apps Rad choose non-clustered CMP Average: 74% over baseline, 55% over simple CMP nc k L1 size/kb energy savings over baseline energy savings over simple CMP Cho % 52.8% Fft % 68.5% fmm % 41.6% luc % 64.4% lun % 58.0% rad % 35.1% ray % 54.9%

22 Energy Optima w/ Performance Requirements 22 Cluster based approach provides best savings Traditional approach only saves energy at high end 53% 20% 32% 22 22

23 Outline 23 Define a new region of operation, Near-Threshold Computing Explore new architectures enabled by key insights of computing in the NTC region Present an initial design of a 3D stacked NTC system, Centip3De 23 23

24 A Closer Look at Wafer-Level Stacking 24 Oxide Silicon Dielectric(SiO2/SiN) Super-Contact Gate Poly STI (Shallow Trench Isolation) W (Tungsten contact & via) Al (M1 M5) Cu (M6, Top Metal) Illustration from Bob Patti, Tezzaron 24 24

25 Next, Stack a Second Wafer & Thin:

26 Then, Stack a Third Wafer: 26 3rd wafer 2nd wafer 1st wafer: controller 26 26

27 Centip3De 3D NTC Prototype 27 Logic - A Logic - B F2F Bond Logic - B Logic - A DRAM Sense/Logic Bond Routing DRAM F2F Bond DRAM Centip3De Design 130nm, 7-Layer 3D-Stacked Chip ARM M3 Cores 150mm

28 Design Scaling and Power Breakdowns 28 NTC Centip3De System 1.9 GOPS (3.8 GOPS in Boost) Max 1 IPC per core 128 Cores 15 MHz 130 mw (691mW in Boost) 14.6 GOPS/W (5.5 in Boost) Naïve Scaling to 22nm yields ~200GOPS/W Boosted Mode Power (mw) NTC Mode Power (mw) Cores I-Caches D-Caches DRAM Raytracing Benchmark 28 28

29 Conclusions 29 Observed Voltage Scaling and Thermal Limits reducing the gains of Moore s Law Defined a new computational operating region: Near Threshold Computing Leveraged key insights of NTC for new clustered architectures Initial ideas of a 3D integrated NTC system, Centip3De 29 29

30 Related References 30 Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester, Trevor Mudge, Near-Threshold Computing: Reclaiming Moore s Law Through Energy Efficient Integrated Circuits, Proceedings of the IEEE, Special Issue on Ultra-Low Power Circuit Technology, Vol. 98, No. 2, February 2010, pg Bo Zhai, Ronald G. Dreslinski, Trevor Mudge, David Blaauw, Dennis Sylvester, Energy Efficent Near-threshold Chip Multi-processing, ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), August 2007, Best Paper Nomination. Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Nam Sung Kim, Krisztian Flautner, Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation, IEEE, Vol. 24, No. 6, November-December 2004, pg Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester, A 0.27V, 30MHz, 17.7nJ/transform 1024-pt complex FFT core with super-pipelining, IEEE International Solid-State Circuits Conference (ISSCC), February 2011, to appear 30 30

31 Backup

32 Logic vs. Memory 32 To maintain same robustness at low voltages SRAM cell sizes needs to be increased to compensate effects of process variation Increased size leads to higher energy consumption, and longer interconnects

33 Proposed Parallel Architecture

34 Energy Optimal Vth Selection Vth is very high Energy optimal Vdd is independent of Vth Free performance gain without consuming more energy As Vth reduces Circuit operates faster More leakage, more energy consumption per switching Choose Vth 34 Body bias Dopant implant