A Non-Volatile Microcontroller with Integrated Floating-Gate Transistors

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1 A Non-Volatile Microcontroller with Integrated Floating-Gate Transistors Wing-kei Yu, Shantanu Rajwade, Sung-En Wang, Bob Lian, G. Edward Suh, Edwin Kan Cornell University

2 2 of 32 Self-Powered Devices Autonomous wireless sensor networks RFIDs and RFID readers In-body sensors and health monitoring

Limited computation Intel WISP active only 27% of the time Source: Kevin Fu, U

3 3 of 32 Computation with Unstable Power Autonomous systems harvest power from environment Many power sources unstable / unreliable Solar Wind RF signal Limited computation Intel WISP active only 27% of the time Source: Kevin Fu, U Mass. Amherst Ex: RF energy trace RF relatively reliable Yet voltage fluctuates wildly

4 4 of 32 Non-Volatile Computing Build non-volatile processors that remember state across power interruptions Benefits Computation across power interruptions Idle time power gating without sacrificing response time Replace or augment volatile structures in processor with non-volatile structures

5 5 of 32 Non-Volatile Processor Processor has non-volatile storage Reserve capacitor Power cut-off at any time On power failure, store to nonvolatile storage (NV store) Power Capacitor Processor On power restoration, load and resume computation (NV restore) Volatile state NV memory

6 6 of 32 Outline Non-volatile processor architecture Hybrid volatile/non-volatile memory cell Prototype microcontroller Results Conclusion

7 7 of 32 Non-volatile Processor Requirements Fast and low-energy NV store and restore Perform NV store with limited energy after power failure Low impact on normal processor operation Long lifetime Minimize program/erase cycles to NV memory

8 8 of 32 Processor Design Options Discrete Fully non-volatile Processing unit Volatile registers NV memory Processing unit NV regs Volatile memory Non-Volatile memory + No impact on normal operation + Infrequent NV operations allow long lifetime Expensive NV store and erase + No NV operation after power failure High penalty on normal operation Short NV memory lifetime

9 9 of 32 Our Approach: Hybrid Architecture Hybrid volatile/non-volatile Per-cell integration of volatile and non-volatile components Enables non-volatile computing Low normal operation penalty Infrequent NV store and erase gives long lifetime Low energy NV store and erase Overheads Area of hybrid cell Energy and delay cost in normal operation Processing unit Hybrid registers Hybrid memory volatile NV cell

10 10 of 32 Outline Non-volatile processor architecture Hybrid volatile/non-volatile memory cell Prototype microcontroller Results Conclusion

11 11 of 32 Nanocrystal Flash Memory Why Flash? No current during program Nanocrystal Flash Long endurance (10 12 cycles) Relatively low voltage (6 V) Fabrication Devices made in lab Freescale has a similar type in production Metal NC (4-10 nm) SiO 2 (2 nm) Gate N-Si SiO 2 (7 nm)

12 of 32 Hybrid Volatile/Non-volatile Memory Combines two memory types at cell-level SRAM and Flash On power failure, data in SRAM is moved to Flash (NV store)

12 12 of 32 Hybrid Volatile/Non-volatile Memory Combines two memory types at cell-level SRAM and Flash On power failure, data in SRAM is moved to Flash (NV store) On power restoration, data moved from Flash to SRAM (NV restore) Also applied to D Flip-flop Data movement for array happens in parallel Memory Array SRAM Flash

13 13 of 32 Hybrid Volatile/Non-volatile Memory Start with an SRAM Augmented with 2 NV Flash transistors Connected to VDD via enable transistors

14 14 of 32 Normal Read and Write Operation Enable and Program/Erase (PE) off Acts identically to SRAM

15 15 of 32 Non-Volatile Store Operation 6V 6V NV store records data from SRAM to Flash Enables OFF PE signal ON, high voltage (6V)

16 16 of 32 Non-Volatile Restore Operation 1V 1V Enables ON The Flash with higher Vth will conduct less current Imbalance in current restores SRAM state

17 17 of 32 Erase -6V -6V Negative high voltage applied to PE node Enables OFF

18 18 of 32 NV D Flip-flop Similar to NV-SRAM in operation

19 19 of 32 Outline Non-volatile processor architecture Hybrid volatile/non-volatile memory cell Prototype microcontroller Results Conclusion

20 20 of 32 Prototype Microcontroller Cond. Inst reg PC GPR (16x8-bit) Processing units (ALU) Program Flash (2KB) Stack (32x10-bit) Scratch pad (64B) 8-bit low power microcontroller Modified Picoblaze clone Similar to microcontrollers in self-powered devices Small enough to perform detailed circuit-level simulation

21 21 of 32 Non-Volatile Architecture Capacitor Power monitor NV control Cond. Inst reg PC GPR (16x8-bit) Processing units (ALU) Charge pumps Program Flash (2KB) Stack (32x10-bit) Scratch pad (64B) Architectural state augmented with hybrid memory NV-DFFs used Additional circuits Power monitor Non-volatile controller Charge pumps

22 22 of 32 Power Failure Energy Consumption Pre-charge pump Maintain charge Power Normal operation Charge pump Charge pump store erase store Power-down Off Time Off

23 23 of 32 Evaluation Study performance, area and energy overheads Compare volatile vs. hybrid non-volatile architecture Hybrid memory study Layout and HSPICE simulation based on experimental data Area, delay, energy estimates System-level study Synopsys + Cadence std. cell flow with HSIM/Verilog co-simulation Normal instruction operation overheads NV save, restore and erase

24 24 of 32 NV Memory Area 63% larger 40% larger Normalized Area Normalized Area SRAM Hybrid NV-SRAM DFF Hybrid NV-DFF

25 25 of 32 NV Memory Energy fj SRAM Read/Write Energy 18% more fj DFF Transition Energy 15% more % more % more Read Write to 1 1 to 0 SRAM Hybrid NV-SRAM DFF Hybrid NV-DFF

26 26 of 32 Cell Delay ps SRAM SRAM Read / Write Delay 18% more Read 16% more Write Hybrid NV-SRAM ps DFF DFF Transition Delay 28% more 0 to 1 1 to 0 Hybrid NV-DFF 38% more

27 27 of 32 Prototype Microcontroller Area 80,587 µm 2 on a 65nm process (w/o program Flash or charge pump, NV controller) 20% larger Normalized Area Baseline Prototype

Normalized Energy Prototype Energy and Performance Each instruction in microcontroller ISA simulated 20x 1.04 1.02 1 0.98 0.96 0.94 0.92 0.9 Average 1.

28 Normalized Energy Prototype Energy and Performance Each instruction in microcontroller ISA simulated 20x Average 1.5% energy increase No impact on clock frequency due to slow operating speed add addcy sub subcy compare and or xor test shiftr0 shiftr1 shiftrx shiftra rotater shiftl0 shiftl1 shiftlx shiftla rotatel load/store call return 28 of 32 baseline hybrid NV

29 29 of 32 NV Operation Energy and Performance Dominated by charge pump energy Total 1Kbits storage Operation Delay Energy NV store 10 µs 172 pj NV restore ~ 5 ns - NV erase ~ 10 µs, background ~ 172 pj

30 30 of 32 Handling Power Interruptions Hybrid NV architecture Store/Erase each need pj / byte Reserve capacitor needed NV store + NV erase 280 pf For larger processors, benefit increases More state to save Discrete off-chip NV architecture Store needs µj / byte Restore needs µj / byte

31 31 of 32 Related Work Hybrid volatile/non-volatile memory Many NV-SRAM designs exist Use resistive memory technology Self-checkpointing microprocessors Off-chip NV memory Periodic snapshots Perpetual embedded devices Platforms targeting ultra-low power operation Still volatile Non-volatile memory in system architecture PCM in DRAM, Flash as hard disk Focus on performance and energy efficiency

32 32 of 32 Summary Non-volatile computing Allows computing in power-limited, embedded devices Compute across power outages Hybrid volatile/non-volatile memory Closely integrates nanocrystal flash Fast, low-energy save / restore Non-volatile microprocessor Fast save and restore on power down / up Less than 2% normal energy overhead 20% area overhead

Novel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors" ASP-DAC 2014

Novel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors" ASP-DAC 2014 Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe Toshiba Corporation, R&D Center Advanced