GST, from Sensor to Decision
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- Sophia Chambers
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1 GST, from Sensor to Decision Videos Signals Mul2Media sound, images 2D, 3D,.. GST: Created in september persons (10 in R&D and 2 in Business) Technology based on neuro-inspired algorithms: E m b e d d e d S y s t e m s b a s e d o n t h e func2oning of the human brain for detec2on and object recogni2on. February 3rd
2 Concerned Applications Ø Surveillance-Security indoor and outdoor (novelty detec2on, face recogni2on, tracking, ) Ø Produc7on automa7on (anomaly detec2on, product selec2on, iden2fica2on, ) Ø Home automa7on (people coun2ng, preven2on of falls for elderly, ) February 3rd 2017 Ø R o b o 7 c s, A u t o m o 7 v e (automated driving, object detec2on and target tracking in movement, ) ADAS (Advanced Driver Assitant Systems) Ø Human-Machine-Interac7on (TV, computers, smart pads, ) 2
3 Videos Signals Mul2Media sound, images 2D, 3D,.. GST Technology: Embedded Neuro-inspired Systems February 3rd 2017 Neuromorphic Compu2ng - Brussels 3
4 Available GST Smart NeuroCam-1 Based on Neuro-FPGA-1 CogniMem CM1K 1024 neurons 752x480 pixels Config serial flash Config ROM FTDI USB controller Xilinx Spartan6 lx16 Exposure Time: SDRAM 512 Mo 100µs to 20ms 4Mo serial flash memory USB February 3rd x test points 88 I/O External supply 4 x LED 4
5 PNeuro accelerator (Joint Laboratory CEA & GST ini2ated in 2013) Objec7ve: Design a processor integra2ng within the same chip signal processing func2ons and neural func2ons: ConvNet (CNN), Hmax, Data In (Signals, Images) Cluster NeuroCores Cluster NeuroCores Cluster NeuroCores Classifica2on Result From Previous PNeuro PNeuro: A Cascadable Parallel Architecture To Next PNeuro February 3rd 2017 Neuromorphic Compu2ng - Brussels 5
6 PNeuro accelerator overview February 3rd 2017 Neuromorphic Compu2ng - Brussels 6
7 PNeuro accelerator: Main Specifica7ons Fully-programmable energy efficient hardware accelerator Designed for DNN processing chains CNN, Hmax Suppor2ng tradi2onal image processing chains (filtering, etc.) Clustered SIMD architecture Op2mized operators for MAC & NL-approxima2on Op2mized memory accesses to perform efficient data transfers to operators ISA including ~50 instruc2ons (control + compu2ng) Programming tools under development Library including most-common kernels with associated parameters (convolu2on, max pooling, fully-connected layers) to ease programming Based on N2D2 placorm with dedicated exports for PNeuro Neuromorphic Compu2ng - Brussels
8 PNeuro on FPGA First demonstra7on on a FPGA-based PNeuro using ConvNet (CNN) Single cluster configura7on (4 Neuro-Cores) Embedded CNN applica2on (60 neurons on the hidden layer, 450 KOps) Faces extrac2on, images (48x48 pixels) on the database, 96% recogni2on rate Same applica2on ported on 5 different architectures Embedded CPU: Raspberry PI 2 B, Odroid Xu3 Embedded GPU: NVidia Tegra K1 (batch) Desktop CPU: Intel I7 PNeuro, Quad Neuro-Cores Using a CEA custom prototyping board FPGA approach is already compe77ve with exis7ng CPU & GPU solu7ons FPGA product developed for early 2017 by GST (NeuroFPGA-2 board) Embedded FPGA: Ar7x 100 (~1W), 17.6cm² for the board, including one cluster Target Freq (MHz) Energy Eff. (Images/s/W) Perf (Images/s) Intel I Quad ARM A Quad ARM A Tegra K PNeuro (FPGA) Neuromorphic Compu2ng - Brussels
9 ASIC EVALUATION Caracteriza2on chip in fabrica2on (tapeout end of june 2016) in FDSOI 28nm Peak performances up to mm² for a single cluster and its control, w i t h a p o w e r c o n s u m p 2 o n u n d e r 35mW@500 MHz
10 GST Roadmap 1D Signals 2D & 3D Images Mul2media Data Data mining ConvNet Hmax Working sta2ons (PC, Mac) à 2012 Embedded System NeuroFPGA à Embedded processor PNeuro à Smartphone & Cloud à 2015 February 3rd 2017
11 For further information or video examples, visit our website GST Sales GST Headquarter Sales Department 23, rue Paul Bert Boulogne, France Tel.: February 3rd 2017 Technical Department 14, rue Pierre de Couber2n Dijon, France 11
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