PULP: an open source hardware-software platform for near-sensor analytics. Luca Benini IIS-ETHZ & DEI-UNIBO

Transcription

1 PULP: an open source hardware-software platform for near-sensor analytics Luca Benini IIS-ETHZ & DEI-UNIBO

2 An IoT System View Sense MEMS IMU MEMS Microphone ULP Imager Analyze µcontroller L2 Memory e.g. CortexM IOs Transmit Short range, BW Low rate (periodic) data EMG/ECG/EIT MOPS 1 10 mw SW update, commands Long range, low BW 100 µw 2 mw cm 2 Harvesting powered mw (MaxP) + uw (AvgP) Idle: ~1µW Active: ~ 10mW 2

3 The Computing Bottleneck Microcontroller Landscape *not exhaustive High performance MCUs Low-Power MCUs Our Target Luca Benini 3

4 Reaching pj/op

5 Content Understanding A general pattern 1. Extract descriptors from raw data 2D: Corners, blobs, 1D: LPC coefficients, Usually highly parallel 2. Use descriptors to classify data among family representatives Machine learning, Bayesian,. Also highly parallel

6 Minimum energy operation Source: Vivek De, INTEL Date nm CMOS, 25 o C Energy/Cycle (nj) X Total Energy Leakage Energy Dynamic Energy Logic Vcc / Memory Vcc (V) Near-Threshold Computing (NTC): 1. Don t waste energy pushing devices in strong inversion 2. Recover performance with parallel execution 6

7 The best Processor [AziziISCA10] Single issue in-order is most energy efficient Put more than one + shared memory to fill cluster area Departement Informationstechnologie und Elektrotechnik 7

8 Near-Threshold Multiprocessing SIMD/MIMD/SEQ Shared L1 I$ + configurable broadcasting I$B 0 I$ I$B k Up to 16 simple cores IL0 IL0 PE PE N 1 LOGARITHMIC INTERCONNECT Private Loop/prefetch buffer DMA MB 0 L1 TCDM MB M Tightly Coupled DMA Shared L1 DataMem +configurable interleaving NT but parallel Max. Energy efficiency when Active + strong PM for (partial) idleness

9 Near threshold FDSOI technology Body bias: Highly effective knob for power management! 9

10 Silicon Results Technology UTBB FD-SOI 28nm Transistors Flip well L = 24 nm Cluster area 1.3 mm 2 VDD range (memories) BB range SRAM macros SCM macros Gates Frequency range Power range 0.32V V ( V) 0V V 8 x 32 kbit (TCDM) 16x4 kbit (TCDM) 4x 2x4 kbit (I$) 200K NO BB: MHz MAX FBB: MHz NO FBB: mw MAX FBB: mw Hot Chips 15 V1 Cool Chips 16 V2 ~5pJ/OP Luca Benini 10

11 Cluster Energy Efficiency MHz, 0.46V, 0V FBB, 840 µw 10 1GOPS, 100 MOPS/mW, 0.66V, 0.5V FBB Full FBB heavily degrades energy efficiency at low voltage due to high Leakage! Luca Benini 11

12 PULP Boards 86.5mm x 57 mm Battery supply PULP Interfaces: JTAG I 2 S UART SPI I 2 C LEDs 128 Mbit Flash Apollo M4 Interfaces: SWD SPI Button I 2 C LEDs GPIO Daughterboard expansions PCB Front PCB Back

13 Open Source Parallel ULP computing for the IoT (sub)-pj/op computing platform - let s make it Open! Processor & Hardware IPs Compiler Infrastructure Virtualization Layer Programming Model 13

14 What has been released RISC-V compatible 32-bit Taped out UMC65nm efficient microprocessor 400MHz core with AXI/AMBA peripherals. RV32I, RV32C supported Most of RV32M (full support soon) Custom extensions (needs our compiler extensions) Hardware loops Post-increment load ALU/MAC instructions Hundreds of GIT forks Confirmed by silicon measurement 14

15 Why Open Hardware? Community Building We want that PULP is used, need a community Cooperation with Academic Partners Allows us to exchange ideas, projects freely We find more partners we can work with Cooperation/supporting Industry Lowers costs for an SME in entering IC business Creates jobs/opportunities (for our students and others) IP, Consulting, Customization Funding Funded Projects Volume Chip production Integrated Systems Laboratory 15

16 Towards fj/op

17 Maximizing Silicon Efficiency GOPS/W > 100 SW Mixed HW General-purpose Computing Throughput Computing 1GOPS/mW CPU GPGPU Accelerator Gap HW IP Closing The Accelerator Efficiency Gap with Agile Customization 17

18 Fractal Heterogeneity Fixed function accelerators have limited reuse how to limit proliferation? 18

19 Learn to Accelerate Brain-inspired systems are high performers in many tasks over many domains. [Honglak Lee] Image recognition [E.g., Krizhevsky et al., 2012] Speech recognition [E.g., Heigold et al., 2013] NLP [E.g., Socher et al., ICML 2011; Collobert & Weston, ICML 2008] 19

20 PULP CNN Accelerator Departement Informationstechnologie und Elektrotechnik 20

21 How do we fare? Spiking-Based mw spiking ops/s/w SIMD-like Convolution ISA Extension GOPS/W IBM TrueNorth [Merolla et al.] PULP + HWCE 0.4V: GOPS/W 0.8V: GOPS/W Convolution Engine [Qadeer et al.] Deep Network ASIC GOPS/W ConvNet FPGA / ASIC up to 230 GOPS/W DianNao [Chen et al.] NeuFlow/nn-X [Gokhale et al.] Ample margins for further improvements