Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab. Scan Testing 2

Transcription

1 MOS INTEGRATE IRUIT EGN TEHNIUES University of Ioannina Scan Testing ept. of omputer Science and Engineering Y. Tsiatouhas MOS Integrated ircuit esign Techniques Overview. Scan testing: design and application 2. At speed testing 3. The scan set set design technique 4. Scan testing power issues 5. The scan hold design technique 6. Level sensitive scan design VL Systems and omputer Architecture Lab 7. Broadcast and Illinois scan design Scan Testing 2

2 Sequential ircuits Testing Inputs outputs = f(inputs, state) Registers State Outputs lock In sequential circuits the initial state (register s values) is not by default known. onsequently, the sensitization of faults and the propagation of the corresponding erroneous responses may turn to be a hard task. A solution is to use techniques for the proper initialization of the circuit state to known values. Application of proper test vector sequences and/or the use of Set/Reset signals to setup the required state. evelopment of efficient techniques to set the initial state and observe the subsequentstateaftertheresponseof the circuit. Scan Testing 3 General Scan Testing Scheme Scan In Registers Inputs Outputs Scan Register lock Scan Out The memory elements (latches or Flip Flops) in a design are properly connected to form a unified shift register (scan register or chain). This way the internal state of the circuit is determined (controlled) by shifting in (scan in) to the scan register the required test data to be applied to the combinational logic. Moreover, the existing internal state (previous logic response) can be observed by shifting out (scan out) thedatastoredintothescan register. Scan Testing 4 2

3 Scan Testing esign (Ι) Primary Inputs Primary Outputs Pseudo Primary Outputs Full Scan Register Original ircuit P Scan In P Pseudo Primary Inputs Scan Register Scan Out Scan Testing 5 Scan Testing esign (ΙI) Multiple Scan hains Partial Scan Scan In_ Scan Register Register Scan In_N... Scan Out_ Scan In Scan Register Scan Register Scan Out_N Scan Out Scan Testing 6 3

4 Scan Path esign (I) Primary In nputs X Z Primary Ou utputs Scan FF Flip Flop 2 M Scan hain Scan Mode = Scan Testing 7 Scan Path esign (II) Primary In nputs X Z Primary Ou utputs 2 M Scan hain Normal Mode = Scan Testing 8 4

5 Test Sequences uring Scan Testing Prima ary Inputs Primary Outputs Test Vector... clock cycles st sequence 2 nd sequence 3 rd sequence 4 th sequence Ν th sequence (Ν+) th sequence Test Response clock cycles Scan Testing 9 Scan Application (Ι) Scan cells testing 2 = Scan in of alternating 3 Μ+ clock cycles and from the input 4 Response observation at the output Μ = # of scan cells Scan Testing 5

6 Scan Application (ΙI) 5 testing 6 = : Test data scan in from the inputs Μ clock cycles (scan in cycles) 7 = : Test pattern application from the inputs 8 Single clock pulse and response observation at the s single clock cycle (capture cycle) Scan Testing Scan Application (ΙII II) 9 = : New test data scan in from the s and simultaneous scan out of the test responses from the s Μ clock cycles Exists another test vector; YES 7 No End Scan Testing 2 6

7 In elay Fault Testing side path Out In2 Out2 path under test V = <> V2 = <> A path delay fault requires a pair of subsequent test vectors to be detected. Thefirsttest test vector initializesthe the circuit while the second test vector activatesthe the pathunder test. How scan testing facilities can be exploited for delay fault testing? Initializing Vector Application Launch Activation Vector Ini alizing test vector Path ac va on test vector Test Response apture At speed clocking! Scan Testing 3 t At Speed Scan Testing (I) (Skewed load or Launch on shift Technique) X Z 2 M Scan hain elay fault oriented scan testing technique Shift Shift Shift unch Lau pture ap Shift Fast Transition t Scan Testing 4 7

8 X At Speed Scan Testing (II) (ouble apture or Launch on apture Technique) Z 2 M Scan hain elay fault oriented scan testing technique Shift Shift unch Lau pture ap Shift ead Time t Scan Testing 5 Fast lock Pulses Generation Scan_ Shift Register PLL PLL_ lock_gating Scan_ PLL_ lock_gating t Scan Testing 6 8

9 The locked Scan Technique X Z K SK K SK 2 K SK M K SK Flip Flop Scan Testing 7 The Scan Set Set Technique (I) X Z 2 M S 2 T 2 M Test ata Scan In = 2= Scan Testing 8 9

10 The Scan Set Set Technique (II) X Z 2 M S 2 T 2 M Test ata Application = 2= Scan Testing 9 The Scan Set Set Technique (III) X Z 2 M S 2 T 2 M Test Response apture = 2= Scan Testing 2

11 The Scan Set Set Technique (IV) X Z 2 M S 2 T 2 M Test Response Scan Out = 2= Scan Testing 2 ual Flip Flops Flops Scan Architecture SB from scan FF SA UPTURE Master Latch 2 2 Flip Flop Scan FF Slave Lth Latch to scan FF from logic UPATE System FF Master Latch Slave Latch 2 2 to logic Intel Scan Testing 22

12 Scan Testing Impact Silicon area and pin count cost. Speed performance degradation. Test application time cost. Excess power consumption (usually outside circuit s specifications) during the scan in/out operations and the capture of the test response in the scan chain. Scan Testing 23 Scan hain Shift Power onsumption (I) apture Test Vector Scan hain Response ycle ycle 2 ycle 3 ycle 4 ycle 5 ycle 6 Scan Testing 24 2

13 Scan hain Shift Power onsumption (II) Test Vector Scan hain Response # Transitions = istance from st scan out bit # Transitions = L (istance from st scan in bit) L = scan chain length Scan Testing 25 Scan hain apture Power onsumption New Response Previous Test Vector Previous Scan hain State Scan hain New Scan hain State Scan hain Power consumption during scan testing procedures is a major concern since it can be several times higher than this during the normal mode of operation. This can affect the reliability of the circuit under test (UT) due to overheat and electromigration phenomena. The excessive switching activity of the UT during the scan operations may violate the power supply IR and Ldi/dt drop limitations and increase the probability of noise induced test failures. In addition, the elevated temperature can degrade the speed performance of the UT and result to erroneous test responses that will invalidate the testing process and lead to yield loss. Scan Testing 26 3

14 X bit Assignment A large number of bits in a test cube that is generated by an ATPG tool are don t care bits (X bits). In order to apply a test cube for circuit testing, specific values must be assigned to the X bits (test vector formation). This task is called X filling. The X filling process can be oriented for shift and/or capture power reduction. Scan Testing 27 Low Power Scan from logic to logic I Scan FF Original Topology from scan FF to scan FF to logic from logic Scan FF Use of ata Gating (φραγμός δεδομένων) techniques at the output t of the scancells in order to eliminate the signal transitions at the inputs of the combinational logic during the scan in/out operations. ynamic power reduction. from scan FF I to scan FF Scan Testing 28 4

15 Scan Hold Flip FlopFlop from logic to logic I Scan FF FF Original Topology from scan FF to scan FF from logic to logic elay testing oriented Flip Flop! + ynamic power reduction. I FF Scan Hold FF Latch from scan hold FF to scan hold FF Hold Scan Testing 29 The Scan Hold Technique X Z A Scan FF A Scan FF A Scan FF Latch 2 Latch M Latch Hold Scan Hold FF Intel Scan Testing 3 5

16 Level Sensitive Scan esign (I) X Z A L A L A L 2 M B L 2 B L 2 B L 2 A B Latches Pair LSS esign IBM Scan Testing 3 Level Sensitive Scan esign (II) X Z A B A B L L 2 A 2 L B 2 L 2 A M B L L 2 Latches Pair LSS esign IBM Scan Testing 32 6

17 Level Sensitive Scan esign (III) Latch _Latch _FF _Latch Latch and Flip Flop operation _FF Edge Triggered Flip Flop l ή A Latches Pair B Non overlapping Scan Testing clocks 33 t Test ata ompression Typically, ATPG tools generate test vectors where only % to 5% of the bits have specified values! On the other hand, test data volume is a major concern for the available bandwidth and the ATEs storage capabilities. Scan hains Test Patterns Low ost ATE ompressed Test ata compressor ec Stimuli. Tes st Responses ompactor ompacted Response Expected Responses omparator hip UT Scan Testing 34 7

18 Linear ecompression ecompressor X Scan hains Z9 Z5 Z Z 9 Z 5 Z X 9 X 7 X 5 X 3 Z Z 6 Z Z 7 Z 3 Z9 X X4 X9 Z5 X3 X7 Z X2 X5 Z X X2 X5 X6 Z6 X X4 Z2 X3 Z X2 X3 X5 X7 X8 Z7 X X2 X5 X6 Z3 X X4 Z2 X3 X7 X Z8 X2 X5 X8 Z4 X X6 X 4 Z2 Z8 Z4 X X 8 X 6 XOR Scan Testing 35 Broadcast & Illinois Scan esign S S 2 S n 2 n Broadcast tscan esign B S_Mode Illinois Scan esign Segment Segment 2 Segment 3 Segment 4 Scan Testing 36 8

19 Reconfigurable Broadcast Scan esign Pin Pin 2 Pin 3 Pin 4 ontrol Scan_hain Scan_hain 2 Scan_hain 3 ynamic Reconfiguration Scan_hain 4 Scan_hain 5 Scan_hain 6 Scan Testing 37 Scan hain Scan hain 2 Space ompaction Scan hain 3 Scan hain 4 SO SO 2 SO 3 SO 4 SO 5 SO 6 SO 7 SO 8 Scan hain 5 Scan hain 6 Scan hain 7 Scan hain 8 Scan chains outputs Linear Phase ompactor X ompact Out Out 2 Out 3 Out 4 Scan Testing 38 9

20 Random Access Scan esign X Z Row (X) ecoder S S. S S. S S. S S S olumn (Y) ecoder TM Scan ell S Address Shift Register AI AS Scan Testing 39 Reordering of Scan hain Flip FlopsFlops (Ι) Typical Scan hain 8FF 4FF 5 TV 3TV 5 Test Vectors 2FF 3 Test Vectors ΙΝ 4FF 2FF Test Application: 3(2+)+2 = 632 clock cycles st Alternative Test Application: 3(4+)+8 = 458 clock cycles Random register connection Improvement 29%! Scan Testing 4 2

21 Reordering of Scan hain Flip FlopsFlops (II) 2 nd Alternative Scan Testing Application 8FF 4FF 5 Test Vectors 2FF 3 Test Vectors ΙΝ 4FF 2FF Test Application: 5(4+) = 75 clock cycles 25(2+)+8 = 3258 clock cycles 48 clock cycles Improvement 37%! Scan Testing 4 Reordering of Scan hain Flip FlopsFlops (III) 3 rd Alternative Scan Testing Application with cell reordering 8FF 4FF 5 Διανύσματα Ελέγχου 2FF 3 Διανύσματα Ελέγχου ΙΝ 4FF 2FF Test Application: 5(8+) = 95 clock cycles In addition, test power reduction is achieved! 25(4+)+4 = 254 clock cycles 224 clock cycles Improvement 65%! Scan Testing 42 2

22 References Principles of Testing Electronics Systems, S. Mourad and Y. Zorian, John Wiley &Sons, 2. Essentials of Electronic Testing: for igital, Memory and Mixed Signal VL ircuits, M. Bushnell and V. Agrawal, Kluwer Academic Publishers, 2. Power onstrained Testing of VL ircuits, N. Nicolici and B. Al Hashimi, Kluwer Academic Publishers, 23. igital Systems Testing and Testable esign, M. Abramovici, M. Breuer and A. Friedman, omputer Science Press,99. System on hip Test Architectures, L T Wang,. Stroud and N. Touba, Morgan Kaufmann, 28. VL Test Principles and Architectures, L T Wang, W. Wu and X. Wen, Morgan Kaufmann, 26. Scan Testing 43 22