Controller Implementation--Part I. Cascading Edge-triggered Flip-Flops. Clock Skew. Cascading Edge-triggered Flip-Flops. Why Gating of Clocks is Bad!

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1 Controller Implementation--Part I lternative controller FSM implementation approaches based on: Classical Moore and Mealy machines Time state: ivide and Jump counters Microprogramming (ROM) based approaches» branch sequencers» horizontal microcode» vertical microcode Cascading Edge-triggered Flip-Flops Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) OUT CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - Cascading Edge-triggered Flip-Flops Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) OUT Clock Skew The problem Correct behavior assumes next state of all storage elements determined by all storage elements at the same time ifficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay) Effect of skew on cascaded flip-flops: elay CS - Spring Lec #: Control Implementation - In original state: =, =, = due to skew, next state becomes: =, =, and not =, = CS - Spring Lec #: Control Implementation - is a delayed version of Why Gating of Clocks is Bad! Why Gating of Clocks is Bad! L L generated by FSM shortly after rising edge of L gated Runt pulse plays HVOC with register internals! GOO L o NOT Mess With Clock Signals! B gatedclk NSTY HCK: delay L through negative edge triggered FF to ensure that it won t change during next positive edge event Ln gated skew PLUS L delayed by half clock cycle What is the effect on your register transfers? o NOT Mess With Clock Signals! CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation -

2 Why Gating of Clocks is Bad! Why Gating of Clocks is Bad! L slowclk B Better! o NOT Mess With Clock Signals! o NOT Mess With Clock Signals! CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - lternative Ways to Implement Processor FSMs "Random " based on Moore and Mealy esign Classical Finite State Machine esign ivide and Conquer pproach: Time-State Method Partition FSM into multiple communicating FSMs Exploit Block Functionality: s, Multiplexers, ecoders Microprogramming: ROM-based methods irect encoding of next states and outputs Random Perhaps poor choice of terms for "classical" FSMs Contrast with structured logic: PL, FPG, ROM-based (latter used in microprogrammed controllers) Could just as easily construct Moore and Mealy machines with these components CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - Moore Machine State iagram RES! PC Memory-ister Interface Timing IF PC! MR, PC +! PC Note capture of MBR in these states IF IF MR! Mem,! Read/Write,! Request, Mem! MBR IF IF IF IF IF IF MBR! IR WIT = = O = = Mem Bus ata Valid IR! MR, L IR! MR ST C! MBR MR! Mem, MR! Mem, L! Read/Write, ST! Read/Write,! Request,! Request, Mem! MBR MBR! Mem L MBR! C IR! MR BR = = MR! Mem, BR! Read/Write, IR! PC! Request, Mem! MBR MBR + C! C Latch MBR Invalid ata Latched Invalid ata Latched Valid ata Latched Valid data latched on IF to IF transition because data must be valid before can go low CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation -

3 Moore Machine iagram IR<> IR<> C<> Moore Machine State Table Clock Next State State Read/Write Request! PC PC +! PC PC! BUS IR! BUS BUS! MR BUS! PC MR! Memory ddress Bus Memory ata Bus! MBR MBR! Memory ata Bus MBR! MBUS MBUS! IR MBUS! LU B MBUS! C RBUS! C RBUS! MBR LU states, bit state register Next State : Inputs, s : Inputs, s These can be implemented via ROM or PL/PL Next State: x bit ROM : x bit ROM IR<> IR<> C<>Current State Next State ister Transfer Ops X X X X X RES () X X X X RES () IF ()! PC X X X X IF () IF () PC! MR, PC +! PC X X X IF () IF () X X X IF () IF () X X X IF () IF () MR! Mem, Read, X X X IF () IF () Request, Mem! MBR X X X IF () IF () MBR! IR X X X IF () O () X X O () L () X X O () ST () X X O () () X X O () BR () CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - Moore Machine State Table IR<> IR<> C<> Current State Next State ister Transfer Ops X X X X L () L () IR! MR X X X L () L () MR! Mem, Read, X X X L () L () Request, Mem! MBR X X X X L () IF () MBR! C X X X X ST () ST () IR! MR, C! MBR X X X ST () ST () MR! Mem, Write, X X X ST () IF () Request, MBR! Mem X X X X () () IR! MR X X X () () MR! Mem, Read, X X X () () Request, Mem! MBR X X X X () IF () MBR + C! C X X X BR () IF () X X X BR () BR () X X X X BR () IF () IR! PC Moore Machine State Transition Table Observations: Extensive use of on't Cares Inputs used only in a small number of state e.g., C<> examined only in BR state IR<:> examined only in O state Some outputs always asserted in a group ROM-based implementations cannot take advantage of don't cares However, ROM-based implementation can skip state assignment step CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - Standard Mealy Machine has asynchronous outputs Change in response to input changes, independent of clock Revise Mealy Machine design so outputs change only on clock edges One approach: non-overlapping clocks Synchronizer Circuitry at Inputs and s ' ' STTE STTE STTE CS - Spring Lec #: Control Implementation - ' ' Case I: Synchronizers at Inputs and s cycle cycle cycle S / S ' S ' asserted in Cycle, becomes asserted after cycle delay! This is clearly overkill! CS - Spring Lec #: Control Implementation -

4 Synchronous Mealy Machine Case II: Synchronizers on Inputs Case III: Synchronized s ' cycle cycle cycle S S / S S '/ cycle cycle cycle S S / ' asserted in Cycle, follows in next cycle Same as using delayed signal (') in Cycle! asserted during Cycle, ' asserted in next cycle Effect of delayed one cycle CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - Implications for Processor FSM lready erived Consider inputs:,, IR<:>, C<> Latter two already come from registers, and are sync'd to clock Possible to load IR with new instruction in one state & perform multiway branch on opcode in next state Best solution for and : synchronized inputs» Place flipflops between these external signals and the» control inputs to the processor FSM» Sync'd versions of and delayed by one clock cycle Time State ivide and Conquer Overview Classical pproach: Monolithic Implementations lternative "ivide & Conquer" pproach:» ecompose FSM into several simpler communicating FSMs» Time state FSM (e.g., IFetch, ecode, Execute)» Instruction state FSM (e.g., L, ST,, BRN)» Condition state FSM (e.g., C <, C # ) CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - Time State (ivide & Conquer) Time State FSM Most instructions follow same basic sequence iffer only in detailed execution sequence Time State FSM can be parameterized by opcode and C states Instruction State: stored in IR<:> Condition State: stored in C<> = = IR = = L ST BRN T T T T T T T BRN C! / (L + ST + ) C<>= C?" BRN + (ST )/ (L + ) C < C<>= T CS - Spring Lec #: Control Implementation - Time State (ivide & Conquer) Generation of Microoperations! PC: PC +! PC: T PC! MR: T MR! Memory ddress Bus: T + T (L + ST + ) Memory ata Bus! MBR: T + T (L + ) MBR! Memory ata Bus: T ST MBR! IR: T MBR! C: T L C! MBR: T ST C + MBR! C: T IR<:>! MR: T (L + ST + ) IR<:>! PC: T BRN! Read/Write: T + T (L + )! Read/Write: T ST! Request: T + T (L + ST + ) CS - Spring Lec #: Control Implementation -

5 Jump Concept Implement FSM using MSI functionality: counters, mux, decoders Pure jump counter: only one of four possible next states CLR N LO N+ XX HOL Single "" function of the current state Pure Jump Inputs Count, Load, Clear Clear Load Count CLOCK Synchronous State ister NOTE: No inputs to jump state logic Hybrid jump counter: Multiple "s" function of current state + inputs blocks implemented via discrete logic, PLs, ROMs CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - Problem with Pure Jump Hybrid Jump ifficult to implement multi-way branches O L ST BR al State iagram Extra States: O L ST O O BR Inputs Count, Load, Clear Load Count CLOCK Clear Synchronous State ister Load inputs are function of state and FSM inputs Pure Jump State iagram CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation - RES Implementation Example IF Implementation Example, Continued State assignment attempts to take advantage of sequential states IF IF O = (s + s + s + s) + (s + s) + (s + s + s + s) = (s + s) + (s + s + s + s) CLR = + s + s + s + (s ) CLR = s s s (s + ) L = s L L L ST ST BR Contents of ROM ddress Contents (Symbolic State) (L) (ST) () (BR) CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation -

6 /S Implementation Example, continued /S /S /S /S /S /S OR IR IR / /S /S /S Cnt PL S S S HOL S S S IR<> IR<> N Implement CLR /S Implement using active lo PL P T RCO C C B B LO CLR / / G G C B CS - Spring Lec #: Control Implementation - NOTE: ctive lo outputs from decoder /S /S /S /S /S /S /S /S /S /S /S /S /S /S /S /S CLR,, L implemented via Mux CLR = CLRm + CLR = CLRm + ctive Lo outputs: hi input inverted at the output Note that is active hi on counter so invert MUX inputs! /CLRm / IR IR /CLR IR<> IR<> / / S S S S /CLR P T RCO C C B B G G G E E E E E E + E + E E E E E E E E E E E E / E E E E EOUT E EOUT EOUT E E /CLRm E E E E E E E E E + E E E E E E E / E E E E E E CS - Spring Lec #: Control Implementation - /L LO CLR S S S S G G C B S S S S /L \S \S \S \S \S \S \S \S \S \S \S \S \S \S Microoperation implementation! PC = PC +! PC = S PC! MR = S MR! Memory ddress Bus = (S + S + S + S + S + S + S + S) Memory ata Bus! MBR = (S + S + S) MBR! Memory ata Bus = (S + S) MBR! IR = S MBR! C = S C! MBR = IR IR S C + MBR! C = S IR<:>! MR = (IR IR + IR IR + IR IR) S IR<:>! PC = C S! Read/Write = (S + S + S + S + S + S)! Read/Write = (S + S)! Request = (S + S + S + S + S + S + S + S) Controller Implementation Summary (Part I!) Control Unit Organization ister transfer operation Classical Moore and Mealy machines Time State pproach Jump Next Time:» Branch Sequencers» Horizontal and Vertical Microprogramming :, CLR, L function of current state + Why not store these as outputs of the ROM? Make and Current State part of ROM address x as many words, bits wide CS - Spring Lec #: Control Implementation - CS - Spring Lec #: Control Implementation -