State of the Union. Krste Asanovic UC Berkeley, RISC-V Foundation, & SiFive Inc.

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1 State of the Union Krste Asanovic UC Berkeley, RISC-V Foundation, & SiFive Inc. 7 th RISC-V Workshop Western Digital, Milpitas, CA November 28, 2017

2 What is RISC-V? A high-quality, license-free, royalty-free RISC ISA specification originally from UC Berkeley Standard maintained by non-profit RISC-V Foundation Suitable for all types of computing system, microcontrollers to supercomputers Numerous proprietary and open-source cores Experiencing rapid uptake in industry and academia Supported by growing shared software ecosystem A work in progress

3 What s Different about RISC-V? Simple - Far smaller than other commercial ISAs Clean-slate design - Clear separation between user and privileged ISA - Avoids µarchitecture or technology-dependent features A modular ISA designed for extensibility/specialization - Small standard base ISA, with multiple standard extensions - Sparse and variable-length instruction encoding for vast opcode space Stable - Base and standard extensions are frozen - Additions via optional extensions, not new versions Community designed - Developed with leading industry/academic experts and software developers 3

4 1 st Rocket tapeout, EOS14, 45nm User ISA v1.0, Raven-1 tapeout (28nm), RVC MS thesis RISC-V ISA project begins RISC-V Timeline RISC-V Foundation Incorporated Privileged Arch, v1.7, RVC v1.7 Hot Chips 2014 User ISA v2.0 IMAFD First Linux Privileged Arch, v st Workshop RV32E, RVC 1.9 Commercial Softcores 1 st Commercial SoC 7 th Workshop You are here Berkeley World 4

5 Modest RISC-V Project Goal Become the industry-standard ISA for all computing devices So, how s it going? 5

6 Industry Adoption Status Large companies adopting RISC-V for deeply embedded controllers in their SoCs ( minion cores ) - NVIDIA are public with this, others in progress privately - Replaces home-grown and commercial cores CTOs across entire value chain of IC suppliers, system providers, service providers, are aware and imagining/evaluating strategies to leverage RISC-V 6

7 Replacing 2 nd -tier ISAs Smaller proprietary-isa soft-core IP companies switching to RISC-V standard to access larger market: - Andes - Codasip - Cortus - others to announce If you re a softcore IP provider, you should have a RISC-V product in development 7

8 Government Adoption India has adopted RISC-V as national ISA US DARPA mandated RISC-V in recent security call for proposals Israel Innovation Authority creating GenPro platform around RISC-V Other countries at various stages of investigation If your country wishes to control security of its own information infrastructure, and further its own domestic semiconductor industry, sponsor RISC-V 8

9 Startups Many startups choosing RISC-V for new products Most are stealthy so will not be visible for at least another year We haven t had to tell startups about RISC-V; they find out pretty quickly when shopping for processor IP 9

10 Commercial Ecosystem Providers A theme at this workshop is mainstream commercial ecosystem support - Express Logic, Imperas, Lauterbach, Micrium, Segger, UltraSOC, Demand is driving supply in commercial ecosystem 10

11 RISC-V in Academic Research Becoming standard ISA for academic research - Celerity >500 RISC-V core SoC in 16nm FinFET - FireSim modeling 1,024 quad-core RISC-V servers in cloud Recent 1st Workshop on Computer Architecture Research using RISC-V (CARRV) at 50th MICRO in Boston was largest workshop (standing room only) even bigger than machine learning tutorial 11

12 RISC-V in Education Available December! Books available now! RISC-V spreading quickly throughout curricula of top schools 12

13 RISC-V: Completing the Innovation Cycle Research Open ecosystem is key to keeping the virtuous cycle going Industry Education 13

14 Foundation: 100+ Members 14 RISC-V Foundation

RISC-V Foundation Growth History August 2015 to November 2017 100 80 60 40 20 0 Q3 2015 Q4 2015 Q1

15 RISC-V Foundation Growth History August 2015 to November Q Q Q Q Q Q Q Q Q Q Platinum Gold Silver Auditor Individual 15

Multiple RISC-V events (outside the Foundation) - CARRV, SoC Conf Irvine, EEWorld

16 Marketing Committee Hired Racepoint Global as Foundation marketing firm Messaging & Marketing Kit released Social Media program active - Regular Twitter & LinkedIn updates Multiple RISC-V events (outside the Foundation) - CARRV, SoC Conf Irvine, EEWorld webinar Website refresh RISC-V news aggregator 7 th Workshop has 15 editors/analysts in attendance 16

17 Upcoming Events RISC-V Tokyo (Dec 18 th, 2017) Embedded World - Have RISC-V booth and day long RISC-V series of talks 8 th RISC-V workshop May 2018 in Barcelona - Other regional events being considered DAC June 2018 HotChips August 2018 Linley Processor Conference October 2018 More to come 17

18 RISC-V Technical Roadmap for 2017 Primary goals were to formally standardize base ISA, memory model, debug, and stabilize privileged architecture for Unix ports and tapeouts Several corners/holes of base ISA fixed, but not quite ratified due to spec versus profiles clarifications - No plans to change any instruction specifications versus 2.0 Unix platform stable as of priv Only backward-compatible changes thereafter 18

19 ISA Specifications and Profiles Original ISA specs mixed instruction specifications with platform mandates - but difficult to agree given wide range of platforms (4KiB microcontroller versus 1TiB Unix server) Now separating instruction set specifications from platform profiles - Maximize reuse of instruction set specifications for different use cases - Constrain profiles more tightly to simplify software compatibility 19

20 Expanded naming of instruction sets Single-letter names will run out someday Need finer-grain naming of instruction sets to describe profiles: - some C instructions depend on F or D being present - how to report multiply not divide implemented? - need to specify potentially dozens of crypto extensions Use Zxxxx to name standard instruction extensions (Xyyy used for non-standard instructions) Existing single-letter names retain meaning In active discussion on isa-dev mailing list 20

21 Profiles for Software Compatibility Software ABI/SBI defines a profile - What harts, registers, instructions, memory are available - How process/os is started/terminated - How I/O happens - For Unix, ABI/SBI assumes IMAFDC=GC instructions Need profiles for M-mode-only microcontrollers - For portable libraries in M-mode and profiles for MU-mode microcontrollers - For each RTOS using M&U modes and for booting MSU platforms Instruction specs reused in all these profiles Aim to have first ready in Q

22 Memory Model Original model was too weak for C11 and also underspecified Amazing work by many experts over course of year We have a resolution: - RVWMO is RISC-V base ISA memory model, weakly ordered - detailed formal specs, both axiomatic and operational! - mapping from C11 to base ISA only, and with A extension - also defined RVTSO as optional extension providing strong TSO memory model (RVTSO strict subset of RVWMO) - see Daniel Lustig s talk later this morning 22

23 ABI and Compilers Calling convention and ABI has been stabilized and documented GCC and binutils have been upstreamed and released in GCC 7.1 (SiFive, Andes) LLVM upstream in progress (lowrisc, Andes) Other compilers/languages: CompCert, Go, Rust, OCaml, Jikes JVM, OpenJDK (not JIT yet), Forth, Pascal, 23

24 Unix Platform Privileged Architecture 1.10 released at last workshop Intent is for future additions to be backwardscompatible with 1.10 Linux port accepted upstream for 4.15 release! FreeBSD mainline since 11.0 Hypervisor spec released - Designed to support recursive virtualization using enhanced S mode See Andrew Waterman s talk next 24

25 Other OS Ports Many other OS ports in progress or completed - FreeRTOS - ZephyrOS - Apache MyNewt - RIOT - sel4 - uc/os - LiteOS - RTEMS - ThreadX - 25

26 Run-Halt Debug Successful collaboration between many organizations has resulted in a stable version awaiting ratification Provides an abstract interface to debug system to support alternative implementation styles Being targeted by commercial ecosystem partners 26

27 Summary of 2017 Technical Roadmap All planned major technical decisions settled Some more work on ratification process needed 27

28 Technical Roadmap Goals for 2018 Complete ratification of base ISA and first profiles - IMADFC, debug specifications - Unix ABI/SBI profiles - M, MU, and MSU-mode platform profiles Base vector extensions proposed and ratified - Validate with compiler support in LLVM, gcc Hypervisor implemented, spec ratified - KVM primary, Beehive and Xen secondary Formal spec completed and released 28

29 Vector Extensions Reconfigurable, vector-length-agnostic, mixed-precision, vector unit that replaces other ISAs packed-simd extensions Ideal for machine learning, DSP, graphics, supercomputing, Considerable movement on design, getting simpler Support for scalar, 1D vector, and 2D matrix shapes of various types (floating, int, 8b, 16b, 32b,.., 512b) Crypto extension builds on wide scalar bit vectors Best Vector ISA Ever Talk tomorrow by Roger Espasa 29

30 Security Really two separable efforts in Foundation: - Trusted execution environments (TEE) - Cryptographic instruction extensions Much other work including MIT Sanctum (enclaves), lowrisc (tagged memory), CHERI (capabilities), Dover (accelerated metadata rules), secure boot (Microsemi, Rambus), RISC-V is dominating security research Everyone agrees security is really important No industry agreement on right solution for everything Work in progress 30

31 Interrupts So far, we have fast local interrupts (per-hart) and global platform-level interrupts (PLIC) Requests from: High-end systems (many cores, complex devices), would like per-hart message-signaled interrupts (MSI) - MSI scheme needs to be developed alongside hypervisor Low-end embedded (slow cores, dumb devices) want preemptive vectored prioritized interrupts - Should not disturb existing schemes 31

32 Improving Embedded Compression C extension was designed for general-purpose computing, with Unix binaries Seeing some non-competitive RISC-V code size on pure embedded workloads Likely due to byte, halfword memory access? - more research needed Considering alternative C for RV32E systems? 32

33 J Extension New task group initiated to explore support for dynamically translated languages (JVM, Javascript, etc.) Handling integer overflow? Garbage collection? Instruction cache management? 33

34 RISC-V Technical Priorities for 2018 Priorities: Ratifying base ISA and profiles, with compliance suites Hypervisor implementations Base vector spec and implementations Trusted execution specs, crypto support Formal model for base ISA Others: Message-signaled interrupts Pre-emptive vectored interrupts Improved compression for embedded Tracing support J extension 34

35 Summary Current RISC-V ecosystem usable for commercial embedded development and simpler Unix uses - Multiple softcore providers, ecosystem tool partners Very rapid development and adoption - By time you decide to do project, support will be there Many silicon projects in pipeline, but still no Unixcapable RISC-V SoC for sale Join community and help push along! 35

36 Questions? 36

State of the Union. Krste Asanovic UC Berkeley, RISC- V Founda?on, & SiFive Inc.

State of the Union. Krste Asanovic UC Berkeley, RISC- V Founda?on, & SiFive Inc. State of the Union Krste Asanovic UC Berkeley, RISC- V Founda?on, & SiFive Inc. krste@berkeley.edu 1st RISC- V Summit Santa Clara Conven?on Center, Santa Clara, CA December 4, 2018 What is RISC- V? A high-