SCRx Family Of The RISC-V Compatible Processor IP
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1 SCRx Family Of The RISC-V Compatible Processor IP Alexander Redkin, CEO 1
2 Outline Company intro SCRx product line overview Extensibility/customization service 2
3 Syntacore introduction IP company, founding member of RISC-V foundation Develops and licenses state-of-the-art RISC-V cores - Initial line is available and shipping to customers - ~3 years of focused RISC-V development - Core team comes from 10+ years of highly-relevant background - SDKs, samples in silicon, full collateral Full service to specialize CPU IP for customer needs - One-stop workload-specific customization for 10x improvements - with tools/compiler support - IP hardening at the required library node - SoC integration and SW migration support 3
4 Syntacore background Company: Est 2015 R&D offices in St.Petersburg and Moscow - Representatives in EMEA, APAC 25+ employees, hiring Team background: 10+ years in the corporate R&D (major semi MNC ) Developed cores and SoC are in the mass productions 15+ tapeouts, nm Expertise: Low-power and high-performance embedded cores and IP ASIP technologies and reconfigurable architectures Architectural exploration & workload characterization Compiler technologies 4
5 SCR1: Compact MCU-class open-source core - Minimal area configuration is ~11 kgates - Outline SCR3: High-performance 32-bit MCU with privilege modes - Competitive characteristics SCR4: 32-bit MCU core with high-performance FPU - IEEE compatible Free SCR5: Efficient mid-range APU/embedded core - 1GHz@28nm, virtual memory, 2-4 cores SMP, Linux Stable designs, immediately available for evaluation SDKs, silicon samples, tools, documentation, support All cores are licensed - Lead customer s SoC is deployed in the field in 2018 Baseline cores: extensible and customizable Additions to the family in progress 5
6 SCRx features at glance 6
![SCR1 Compact MCU core for deeply embedded applications RV32I E[MC] ISA <15 kgates in basic untethered configuration (RV32EC) 2 to 4 stages pipeline M-mode only Optional configurable IPIC Free - 8.](/docs-images/81/84254315/images/7-0.jpg ".32 IRQs - OpenOCD compatible - Area- or performance- optimized Optional integrated Debug Controller Choices of the optional MUL/DIV unit Open sourced under SHL-license (Apache 2.")
7 SCR1 Compact MCU core for deeply embedded applications RV32I E[MC] ISA <15 kgates in basic untethered configuration (RV32EC) 2 to 4 stages pipeline M-mode only Optional configurable IPIC Free IRQs - OpenOCD compatible - Area- or performance- optimized Optional integrated Debug Controller Choices of the optional MUL/DIV unit Open sourced under SHL-license (Apache 2.0 derivative with HW specific) - Unrestricted commercial use allowed High quality free MCU IP - Regular updates as specs make progress - In the top 3 System Verilog Github repos Commercial support offered Performance*, per MHz DMIPS -O best** 1.73 Coremark -best** 2.78 * Dhrystone 2.1, Coremark 1.0, GCC 7.1 BM from TCM ** -O3 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto Synthesis data: Minimal RV32EC config: 11 kgates Default RV32IMC config: 32 kgates 250+ tsmc90lp {typical, 1.0V, +25C} 7
8 SCR1 SDK Repository contents: docs - SDK documentation fpga - SCR1 SDK FPGA projects images - precompiled binary files scr1 - SCR1 core source files - sw sample SW projects Supported platforms: Software: Digilent Arty (Xilinx) Terasic DE10-Lite (Intel) - Arria V GX Starter (Intel) Bootloader Zephyr OS Tests/sample apps - Pre-built GCC-based toolchain (Win/Linux) 8
9 SCR1 support Best-effort support provided - scr1@syntacore.com - academic/research use encouraged SLA-based commercial support available - Optimal configuration - Integration into SoC - Integration at client-specific SDK boards - Tapeout support at the target node - Compiler/development tools - Customization service 9
10 SCR3 High-performance MCU-class core with privilege modes RV32I, optional M and C extensions Machine and User privilege modes Optional MPU (Memory Protection Unit) Tightly Coupled Memory (TCM) support KB Optional split L1 caches with ECC 32bit AHB or AXI4 external interface Optional high-performance or area-optimized MUL/DIV unit Optimized for area and power Integrated IRQ controller Performance*, per MHz Advanced debug with JTAG i/f -O DMIPS -best** Coremark -best** 3.30 * Dhrystone 2.1, Coremark 1.0, GCC 7.1 BM from TCM ** -O3 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto 10
![SCR4 MCU-class core with high-performance FPU RV32IMCF[D] ISA Configurable advanced BP, fast MUL/DIV Integrated IRQ controller U- and M-mode 32- or 64bit bit AHB or AXI4 external interface Optional](/docs-images/81/84254315/images/11-0.jpg "MPU Optional configurable TCM, L1 caches Advanced debug controller with JTAG i/f Configurable SP or DP FPU - IEEE 754-2008 compliant Performance*, per MHz DMIPS -O2 1.86 -best** 2.")
11 SCR4 MCU-class core with high-performance FPU RV32IMCF[D] ISA Configurable advanced BP, fast MUL/DIV Integrated IRQ controller U- and M-mode 32- or 64bit bit AHB or AXI4 external interface Optional MPU Optional configurable TCM, L1 caches Advanced debug controller with JTAG i/f Configurable SP or DP FPU - IEEE compliant Performance*, per MHz DMIPS -O best** 2.96 Coremark -best** 3.30 DP Whetstone -best** 1.22 * Dhrystone 2.1, Coremark 1.0, GCC 7.1 BM from TCM ** -O3 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto 11
![SCR5 Efficient mid-range APU/embedded core RV32IMС[AFD] ISA, 64bit option Single-, dual- and quad-core SMP configurations Advanced](/docs-images/81/84254315/images/12-0.jpg "BP (BTB/BHT/RAS), IRQ controller, JTAG debug M-, S- and U-modes Virtual memory support, full MMU L1, L2 caches with coherency,")
12 SCR5 Efficient mid-range APU/embedded core RV32IMС[AFD] ISA, 64bit option Single-, dual- and quad-core SMP configurations Advanced BP (BTB/BHT/RAS), IRQ controller, JTAG debug M-, S- and U-modes Virtual memory support, full MMU L1, L2 caches with coherency, atomics High performance double-precision FPU Linux and FreeBSD support Performance*, per MHz -O2 1,60 DMIPS -best** 2,48 Coremark -best** 2,83 * Dhrystone 2.1, Coremark 1.0, GCC 7.1 BM from TCM ** O3-funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto 12
13 SW development tools IDE in production: GCC GNU Binutils Newlib GNU GDB Open On-Chip Debugger Eclipse Hosts: Linux, Windows Targets: BM, Linux (beta) Also available: LLVM 5.0 CompCert 2.6 Simulators: Qemu Spike Debug solution: Segger J-link, Olimex ARM-USB-OCD family, Digilink JTAG-HS2 supported, Lauterbach H2 18 In progress 13
14 SCR3 SDK Example Integrated IDE/debug solution: GCC (upstream) GNU Binutils (upstream) Newlib GNU GDB Open On-Chip Debugger Eclipse IDE Standard FPGA-based devkit board Number of boards supported (Arria V, Artix-7, others) Low-cost JTAG probe cables Open design Software: First stage bootloader Zephyr/FreeRTOS, others on request Sample applications, tests, benchmarks s/boards-and-kits/1-6olhwl.html s/boards_and_kits/devkits/altera/kit-arria-v-starter.html 14
15 SCR5 SDK Example Integrated IDE/debug solution: GCC (upstream) GNU Binutils (upstream) Glibc 2.22 GNU GDB Open On-Chip Debugger Eclipse IDE Standard FPGA-based devkit board Number of boards supported (Arria 10, Virtex US+) Low-cost JTAG probe cables Open design Software: First stage bootloader SMP Linux (4.x kernel) Sample applications, tests, benchmarks nd_kits/dev-kits/altera/kit-a10-gx-fpga.html 15
16 Evaluation SCR1 Is fully open SCR3-4-5 Full package can be provided under simple evaluation agreement 16
17 Dynamic power Extensibility/customization: how it works Customized core General-purpose core Full energy Full energy Processing time 17
18 Workload-specific customization Extensibility features: Computational capabilities New functions with existing HW New Functional Units Extended storage Mems/RF, addressable or state Custom AGU I/O ports Specialized system behavior Standard events processing Custom events Domain examples: Computationally intensive algorithms acceleration Specialized processors (including DSP) High-throughput applications Wire Speed Processing/ DPI/Real-time/Comms 18
19 SCRx extensibility example Custom ISA extension for AES & other crypto kernels acceleration for SCR5 Data: - RV32G FPGA-based devkit, g , Linux 4.6, optimized C++ implementation - Rv32G + custom same + intrinsics - Core i7 3.4GHz, g , Linux 64, optimized C++ implementation x modest area increase: 11.7% core, 3.7% at the CPU cluster level Encoding throughput, MB/s Normalized per MHz, MB/s RV32G + custom Platform Fmax, MHz Crypto-1 Crypto-2 AES-128 Crypto-1 Crypto-2 AES-128 speed-up RV32G RV32G + custom Core i Core i7 + NI Disclaimer: Authors are aware AES allows for more efficient dedicated accelerators designs, used as example algorithm 19
20 RISC-V Foundation at DAC Visit the RISC-V Foundation booth (West Hall, Level Two at Booth No. 2638). Drinks will be served at the booth on Monday, June 25 and Tuesday, June 26. Join the RISC-V Foundation scavenger hunt for a chance to win prizes (visit booth for details). Attend the poster presentations from member companies at the booth from Monday, June 25, to Wednesday, June 27. See complete schedule on the last slide. 20
21 RISC-V Foundation at DAC Join the RISC-V Ecosystem Reshaping The CPU Landscape workshop on June 24 from 1 p.m. to 4 p.m. PT in Room No. 3018: - RISC-V ISA and Foundation Overview Rick O Connor, RISC-V Foundation - RISC-V A Diversity of Core and Accelerator Choices Markus Levy, NXP - RISC-V OS Landscape Palmer Dabbelt, SiFive - Designing a custom RISC-V core using Chisel Alex Badicioiu, NXP Members of the RISC-V Foundation are participating in additional sessions including: - Core Choices: How To Navigate The Brave New World Of IP (Panel) - A New Golden Age For Computer Architecture: Domain Specific Accelerators And Open RISC-V (Keynote) - PULP-HD: Accelerating Brain-Inspired High-Dimensional Computing on a Parallel Ultra-Low Power Platform (Research Reviewed) - Computing Minus Moore s Law =?!?! (Panel) To learn more, please visit: 21
22 Poster Presentations Schedule Monday, June 25, 2018 Tuesday, June 26, 2018 Wednesday, June 27, a.m. PT RISC-V ISA & Foundation Overview Rick O Connor, RISC-V Foundation 11 a.m. PT RISC-V ISA & Foundation Overview Rick O Connor, RISC-V Foundation 11 a.m. PT Fueling The RISC-V Ecosystem With Microsemi s Mi-V Programmable Solutions Ted Marena, Microsemi Corporation Noon PT 1 p.m. PT 2 p.m. PT 3 p.m. PT From Lab to Fab: An IP Story Panel: Meet The RISC-V Members at DAC 2018 Fueling the RISC-V Ecosystem With Microsemi s Mi-V Programmable Solutions Machine Learning With RISC-V Drew Barbier, SiFive Ted Marena, Microsemi Filip Blagojevic, Western Digital Noon PT It s Not Just the Core, It s the System: Processor Trace in a Holistic World 1 p.m. PT Panel: The Key Role For The Commercial Software Tools Ecosystem For RISC-V 2 p.m. PT RISC-V Support for Persistent Memory Systems 3 p.m. PT RISC-V Virtual Platforms, Simulators and Software Tools Randy Fish, UltraSoC Technologies Matheus Ogleari, Western Digital Simon Davidmann, Imperas Software Noon PT SCRx family of the RISC-V Compatible Processor IP 1 p.m. PT Panel: New Markets and Applications for RISC-V Alexander Redkin, Syntacore 4 p.m. PT 4:30 p.m. PT 5 p.m. PT It s Not Just the Core, It s the System: Processor Trace in a Holistic World RISC-V Virtual Platforms, Simulators and Software Tools Enabling Innovation in Embedded and Enterprise Data-Centric Architectures; Networking Event; Daily Prize Draw Randy Fish, UltraSoC Technologies Simon Davidmann, Imperas Software 4 p.m. PT Introducing the Latest RISC-V Core IP Series 4:30 p.m. PT SCRx Family of the RISC-V Compatible Processor IP Drew Barbier, SiFive Alexander Redkin, Syntacore 2 p.m. PT Panel: Meet the RISC-V Foundation Board Of Directors 3 p.m. PT RISC-V ISA & Foundation Zvonimir Bandic, 5 p.m. PT Keynote on Vision and Yunsup Lee, SiFive Overview; Daily Prize Draw Western Digital History of RISC-V; Networking Event; Daily Prize Draw Rick O Connor, RISC- V Foundation 22
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