Freescale Semiconductor, I APPENDIX B PROGRAMMING SHEETS

Transcription

1 APPENDIX B PROGRAMMING SHEETS The following pages are a set of programming sheets intended to simplify programming the various DSP56002 programmable registers. The registers are grouped between the central processing module and each peripheral. Each register includes the name, address, reset value, and meaning of each bit. The sheets provide room to write the value for each bit and the hexadecimal equivalent for each register. MOTOROLA B - 1

2 SECTION CONTENTS B.1 PERIPHERAL ADDRESSES B-3 B.2 INTERRUPT VECTOR ADDRESSES B-4 B.3 INSTRUCTIONS B-5 B.4 CENTRAL PROCESSOR B-10 B.5 GP I/O B-14 B.6 HOST B-16 B.7 SCI B-21 B.8 SSI B-24 B.9 TIMER B-27 B - 2 MOTOROLA

3 X:$FFFF X:$FFFE X:$FFFD X:$FFFC X:$FFFB X:$FFFA X:$FFF9 X:$FFF8 X:$FFF7 X:$FFF6 X:$FFF5 X:$FFF4 X:$FFF3 X:$FFF2 X:$FFF1 X:$FFF0 X:$FFEF X:$FFEE X:$FFED X:$FFEC X:$FFEB X:$FFEA X:$FFE9 X:$FFE8 X:$FFE7 X:$FFE6 X:$FFE5 X:$FFE4 X:$FFE3 X:$FFE2 X:$FFE1 X:$FFE0 X:$FFDF X:$FFDE PERIPHERAL ADDRESSES INTERRUPT PRIORITY REGISTER (IPR) PORT A BUS CONTROL REGISTER (BCR) PLL CONTROL REGISTER OnCE GDB REGISTER RESERVED RESERVED RESERVED RESERVED RESERVED SCI HI - REC/XMIT DATA REGISTER (SRX/STX) SCI MID - REC/XMIT DATA REGISTER (SRX/STX) SCI LOW - REC/XMIT DATA REGISTER (SRX/STX) SCI TRANSMIT DATA ADDRESS REGISTER (STXA) SCI CONTROL REGISTER (SCCR) SCI INTERFACE STATUS REGISTER (SSR) SCI INTERFACE CONTROL REGISTER (SCR) SSI RECIEVE/TRANSMIT DATA REGISTER (RX/TX) SSI STATUS/TIME SLOT REGISTER (SSISR/TSR) SSI CONTROL REGISTER B (CRB) SSI CONTROL REGISTER A (CRA) HOST RECEIVE/TRANSMIT REGISTER (HRX/HTX) RESERVED HOST STATUS REGISTER (HSR) HOST CONTROL REGISTER (HCR) RESERVED RESERVED PORT C DATA REGISTER (PCD) PORT B DATA REGISTER (PBD) PORT C DATA DIRECTION REGISTER (PCDDR) PORT B DATA DIRECTION REGISTER (PBDDR) PORT C CONTROL REGISTER (PCC) PORT B CONTROL REGISTER (PBC) TIMER COUNT REGISTER (TCR) TIMER CONTROL/STATUS REGISTER (TCSR) X:$FFC0 RESERVED Figure B-1 On-chip Peripheral Memory Map = Read as random number; write as don t care. MOTOROLA B - 3

4 INTERRUPT VECTOR ADDRESSES Table B-1 Interrupts Starting Addresses and Sources Interrupt Starting Address IPL Interrupt Source $ Hardware RESET $ Stack Error $ Trace $ SWI $ IRQA $000A 0-2 IRQB $000C 0-2 SSI Receive Data $000E 0-2 SSI Receive Data with Exception Status $ SSI Transmit Data $ SSI Transmit Data with Exception Status $ SCI Receive Data $ SCI Receive Data with Exception Status $ SCI Transmit Data $001A 0-2 SCI Idle Line $001C 0-2 SCI Timer $001E 3 NMI $ Host Receive Data $ Host Transmit Data $ Host Command (default) $ Available for Host Command $003A 0-2 Available for Host Command $003C 0-2 Timer $003E 3 Illegal Instruction $ Available for Host Command $007E 0-2 Available for Host Command B - 4 MOTOROLA

5 INSTRUCTIONS Table B-2 Instruction Set Summary Sheet 1 of 5 Mnemonic Syntax Parallel Moves Instruction Osc. Program Clock Words Cycles S LE UNZVC ABS D (parallel move) mv 2+mv - ADC S,D (parallel move) mv 2+mv ADD S,D (parallel move) mv 2+mv ADDL S,D (parallel move) mv 2+mv? ADDR S,D (parallel move) mv 2+mv AND S,D (parallel move) mv 2+mv - -?? 0- AND(I) #xx,d ???????? ASL D (parallel move) mv 2+mv?? ASR D (parallel move) mv 2+mv 0? BCHG #n,x:<aa> ea 4+mvb???????? #n,x:<pp> #n,x:<ea> #n,y:<aa> #n,y:<pp> #n,y:<ea> #n,d BCLR #n,x:<aa> ea 4+mvb???????? #n,x:<pp> #n,x:<ea> #n,y:<aa> #n,y:<pp> #n,y:<ea> #n,d BSET #n,x:<aa> ea 4+mvb???????? #n,x:<pp> #n,x:<ea> #n,y:<aa> #n,y:<pp> #n,y:<ea> #n,d BTST #n,x:<aa> ea 4+mvb ? #n,x:<pp> #n,x:<ea> #n,y:<aa> #n,y:<pp> #n,y:<ea> #n,d CLR D (parallel move) mv 2+mv?????- CMP S1,S2 (parallel move) mv 2+mv CMPM S1,S2 (parallel move) mv 2+mv DEBUG DEBUGcc DEC D DIV S,D ?? MOTOROLA B - 5

6 INSTRUCTIONS Table B-2 Instruction Set Summary Sheet 2 of 5 Mnemonic Syntax Parallel Moves Instruction Osc. Program Clock Words Cycles S LE UNZVC DO X:<ea>,expr mv X:<aa>,expr Y:<ea>,expr Y:<aa>,expr #xxx,expr S,expr ENDDO EOR S,D (parallel move) mv 2+mv - -?? 0- ILLEGAL INC D Jcc xxx ea 4+jx JCLR #n,x:<ea>,xxxx jx #n,x:<aa>,xxxx #n,x:<pp>,xxxx #n,y:<ea>,xxxx #n,y:<aa>,xxxx #n,y:<pp>,xxxx #n,s,xxxx JMP xxxx ea 4+jx ea JScc xxxx ea 4+jx ea JSCLR #n,x:<ea>,xxxx jx #n,x:<aa>,xxxx #n,x:<pp>,xxxx #n,y:<ea>,xxxx #n,y:<aa>,xxxx #n,y:<pp>,xxxx #n,s,xxxx JSET #n,x:<ea>,xxxx jx #n,x:<aa>,xxxx #n,x:<pp>,xxxx #n,y:<ea>,xxxx #n,y:<aa>,xxxx #n,y:<pp>,xxxx #n,s,xxxx JSR xxx ea 4+jx ea JSSET #n,x:<ea>,xxxx jx #n,x:<aa>,xxxx #n,x:<pp>,xxxx #n,y:<ea>,xxxx #n,y:<aa>,xxxx #n,y:<pp>,xxxx #n,s,xxxx LSL D (parallel move) mv 2+mv - -?? 0? LSR D (parallel move) mv 2+mv - -?? 0? LUA <ea>,d MAC (+)S2,S1,D (parallel move) mv 2+mv - (+)S1,S2,D (parallel move) (+)S,#n,D (no parallel move) B - 6 MOTOROLA

7 INSTRUCTIONS Table B-2 Instruction Set Summary Sheet 3 of 5 Mnemonic Syntax Parallel Moves Instruction Osc. Program Clock Words Cycles S LE UNZVC MACR (+)S2,S1,D (+)S1,S2,D (parallel move) mv 2+mv (parallel move) - (+)S,#n,D (no parallel move) MOVE S,D mv 2+mv No parallel data move (...) mv mv Immediate short (...)#xx,d mv mv data move Register to register (...)S,D mv mv data move Address register update (...)ea mv mv X memory data move (...)X:<ea>,D mv mv (...)X:<aa>,D (...)S,X:<ea> (...)S,X:<aa> (...)#xxxxxx,d X memory and register (...)X:<ea>,D1 S2,D mv mv data move (...)S1,X:<ea> S2,D2 (...)#xxxxxx,d1 S2,D2 (...)A,X:<ea> X0,A (...)B,X:<ea> X0,B Y memory data move (...)Y:<ea>,D mv mv (...)Y:<aa>,D (...)S,Y:<ea> (...)S,Y:<aa> (...)#xxxxxx,d Register and Y memory (...)S1,D1 Y:<ea>,D2. mv mv data move (...)S1,D1 S2,Y:<ea> (...)S1,D1 #xxxxxx,d2 (...)Y0,A A,Y:<ea> (...)Y0,B B,Y:<ea> Long memory data move (...)L:<ea>,D mv mv (...)L:<aa>,D (...)S,L:<ea> (...)S,L:<aa> XY memory data move (...)X:<eax>,D1 Y:<eay>,D2. mv mv (...)X:<eax>,D1 S2,Y:<eay> (...)S1,X:<eax> Y:<eay>,D2 (...)S1,X:<eax> S2,Y:<eay> MOVE(C) X:<ea>,D ea 2+mvc???????? X:<aa>,D1 S1,X:<ea> S1,X:<aa> Y:<ea>,D1 Y:<aa>,D1 S1,Y:<ea> S1,Y:<aa> S1,D2 S2,D1 #xxxx,d1 #xx,d1 MOTOROLA B - 7

8 INSTRUCTIONS Table B-2 Instruction Set Summary Sheet 4 of 5 Mnemonic Syntax Parallel Moves Instruction Osc. Program Clock Words Cycles S LE UNZVC MOVE(M) P:<ea>,D ea 2+mvm???????? S,P:<ea> S,P:<aa> P:<aa>,D MOVE(P) X:<pp>,D ea 2+mvp???????? X:<pp>,X:<ea> X:<pp>,Y:<ea> X:<pp>,P:<ea> S,X:<pp> #xxxxxx,x:<pp> X:<ea>,X:<pp> Y:<ea>,X:<pp> P:<ea>,X:<pp> Y:<pp>,D Y:<pp>,X:<ea> Y:<pp>,Y:<ea> Y:<pp>,P:<ea> S,Y:<pp> #xxxxxx,y:<pp> X:<ea>,Y:<pp> Y:<ea>,Y:<pp> P:<ea>,Y:<pp> MPY (+)S2,S1,D (+)S1,S2,D (parallel move) mv (parallel move) 2+mv - (+)S,#n,D (no parallel move) MPYR (+)S2,S1,D (parallel move) mv 2+mv - (+)S1,S2,D (parallel move) (+)S,#n,D (no parallel move) NEG D (parallel move) mv 2+mv - NOP NORM Rn,D ?- NOT D (parallel move) mv 2+mv - -?? 0- OR S,D (parallel move) mv 2+mv - -?? 0- ORI #xx,d ???????? REP X:<ea> mv?? X:<aa> Y:<ea> Y:<aa> S #xxx B - 8 MOTOROLA

9 INSTRUCTIONS Table B-2 Instruction Set Summary Sheet 5 of 5 Mnemonic Syntax Parallel Moves Instruction Osc. Program Clock Words Cycles S LE UNZVC RESET RND D (parallel move) mv 2+mv - ROL D (parallel move) mv 2+mv - -?? 0? ROR D (parallel move) mv 2+mv - -?? 0? RTI rx???????? RTS rx SBC S,D (parallel move) mv 2+mv STOP n/a SUB S,D (parallel move) mv 2+mv SUBL S,D (parallel move) mv 2+mv? SUBR S,D (parallel move) mv 2+mv SWI Tcc S1,D S1,D1 S2,D2 TFR S,D (parallel move) mv 2+mv TST S (parallel move) mv 2+mv 0- WAIT n/a NOTATION: - denotes the bit is unaffected by the operation. denotes the bit may be set according to the definition, depending on parallel move conditions.? denotes the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD). 0 denotes the bit is cleared. MOTOROLA B - 9

10 Application: CENTRAL PROCESSOR Date: Sheet 1 of 3 Carry Overflow Zero Negative Unnormalized Extension Limit FFT Scaling Interrupt Mask Scaling Mode Reserved Trace Mode Double Precision Multiply Mode Loop Flag Status Register (SR) Read/Write 0 Reset = $0300 Port A Bus Control Register (BCR) X:$FFFE Read/Write LF DM T S1 S0 I1 I0 S L E U N Z V C Mode Register (MR) Condition Code Register (CCR) Figure B-2 Status Register (SR) EXTERNAL X MEMORY EXTERNAL Y MEMORY EXTERNAL P MEMORY EXTERNAL I/0 MEMORY Figure B-3 Bus Control Register (BCR) B - 10 MOTOROLA

11 MOTOROLA B - 11 CENTRAL PROCESSOR Host IPL HPL1 HPL0 Enabled IPL 0 0 No 0 1 Yes Yes Yes 2 IRQA Mode IAL2 Trigger IAL1 IAL0 Enabled IPL 0 Level 0 0 No 1 Neg. Edge 0 1 Yes Yes Yes 2 SSI IPL SSL1 SSL0 Enabled IPL 0 0 No 0 1 Yes Yes Yes 2 IRQB Mode IBL2 Trigger IBL1 IBL0 Enabled IPL 0 Level 0 0 No 1 Neg. Edge 0 1 Yes Yes Yes 2 SCI IPL SCL1 SCL0 Enabled IPL 0 0 No 0 1 Yes Yes Yes 2 Interrupt Priority Register (IPR) X:$FFFF Read/Write SCL1 SCL0 SSL1 SSL0 HPL1 HPL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL $0 $0 Figure B-4 Interrupt Priority Register (IPR) Application: Date: Sheet 2 of 3

12 B - 12 MOTOROLA CENTRAL PROCESSOR Data ROM Enable 0 = Disable ROMs 1 = Enable ROMs Internal Y Memory Disable 0 = Y Memory controlled by DE bit 1 = All Y Memory external Mode M M M Operating Mode C B A Single-Chip Mode Bootstrap from EPROM Normal Expanded Mode Development Mode Reserved Bootstrap from Host Bootstrap from SCI (external clock) Reserved for Bootstrap Stop Delay 0 = 128K T Stabilization 1 = 16 T Stabilization Operating Mode Register (OMR) Read/Write $0 $0 SD MC MB MA $0 $0 0 = Bit 5 and bits 7 through are reserved. Program as zero 0 YD DE Figure B-5 Operating Mode Register (OMR) Application: Date: Sheet 3 of 3

13 MOTOROLA B - 13 CENTRAL PROCESSOR XTAL Disable Bit (XTLD) 0 = Enable XTAL 1 = Disable XTAL STOP Processing State Bit (PSTP) 0 = PLL Disabled During STOP Processing State 1 = PLL Enabled During STOP Processing State Multiplication Factor Bits MF0 - MF11 MF11 - MF0 Multiplication Factor MF $000 1 $001 2 $ $FFE 4095 $FFF 4096 Clock Output Disable Bits COD0 - COD1 COD1 COD0 CLKOUT Pin 0 0 Clock Out Enabled, Full Strength Output Buffer 0 1 Clock Out Enabled, 2/3 Strength Output Buffer 1 0 Clock Out Enabled, 1/3 Strength Output Buffer 1 1 Clock Out Disabled Chip Clock Source Bit (CSRC) 0 = Output from Low Power Divider 1 = Output from VCO CKOUT Clock Source Bit (CKOS) 0 = Output from LPD 1 = Output from VCO PLL Enable Bit (PEN) 0 = Disable PLL 1 = Enable PLL Division Factor Bits DF0 - DF3 DF3 - DF0 Division Factor DF $0 2 0 $1 2 1 $ $E 2 14 $F 2 15 PLL Control Register (PCTL) X:$FFFD Read/Write Reset = $0X CKOS CSRC COD1 COD0 PEN PSTP XTLD DF3 DF2 DF1 DF0 MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MF0 Figure B-6 PLL Control Register (PCTL) Application: Date: Sheet 1 of 1

14 Application: GP I/O Port B Date: Sheet 1 of 2 PBC1 PBC0 Function 0 0 General Purpose I/O (Reset Condition) 0 1 Host Interface 1 0 Host Interface (with HACK pin as GPIO) 1 1 Reserved Port B Control Register (PBC) X:$FFE0 Read/Write Port B Data Direction Register (PBDDR) X:$FFE2 Read/Write $0 $0 $0 Port B Data Direction Control 0 = Input 1 = Output PBC1 PBC0 Figure B-7 Port B Control Register (PBC) 0 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 0 Figure B-8 Port B Data Direction Register (PBDDR) Port B Data (usually loaded by program) Port B Data Register (PBD) X:$FFE4 Read/Write 0 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 0 Figure B-9 Port B Data Register (PBD) B - 14 MOTOROLA

15 Application: GP I/O Port C Date: Port C Pin Control 0 = General Purpose I/O Pin 1 = Peripheral Pin Sheet 2 of 2 Port C Control Register (PCC) X:$FFE1 Read/Write Port C Data Direction Register (PCDDR) X:$FFE3 Read/Write 0 0 Port C Data Direction Control 0 = Input 1 = Output 0 0 $ $ SSI SCI STD SRD SCK SC2 SC1 SC0 SCLK TXD RXD Figure B-10 Port C Control Register (PCC) CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 Figure B-11 Port C Data Direction Register (PCDDR) Port C Data (usually loaded by program) Port C Data Register (PCD) X:$FFE5 Read/Write $ PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Figure B-12 Port C Data Register (PCD) MOTOROLA B - 15

16 Application: Date: Sheet 1 of 5 HOST Port B Port B Control Register (PBC) X:$FFE0 Read/Write 0 PBC1 PBC0 Function 0 0 General Purpose I/O (Reset Condition) 0 1 Host Interface 1 0 Host Interface (with HACK pin as GPIO) 1 1 Reserved $0 $0 $0 Figure B-13 Port B Control Register (PBC) DSP SIDE Host Receive Interrupt Enable 0 = Disable1 = Enable Interrupt on HRDF Host Transmit Interrupt Enable 0 = Disable1 = Enable Interrupt on HTDE Host Command Interrupt Enable 0 = Disable1 = Enable Interrupt on HCP Host Flags General Purpose Read/Write Flags PBC1 PBC0 Host Control Register (HCR) X:$FFE8 Read/Write Reset = $ HF3 HF2 HCIE HTIE HRIE Figure B-14 Host Control Register (HCR) B - 16 MOTOROLA

17 Application: HOST DSP SIDE Host Receive Data Full 0 = Wait 1 = Read Host Transmit Data Empty 0 = Wait 1 = Write Date: Sheet 2 of 5 Host Status Register (HSR) X:$FFE9 Read Only Reset = $ Host Receive Data Register (HRX) X:$FFEB Read Only RECEIVE HIGH BYTE Host Command Pending 0 = Wait 1 = Ready Host Flags Read Only DMA Status (Read Only) 0 = Disabled 1 = Enabled HF1 HF0 HCP HTDE HRDF Figure B-15 Host Status Register (HSR) 7 DMA Host Receive Data (usually Read by program) RECEIVE MIDDLE BYTE RECEIVE LOW BYTE Figure B-16 Host Receive Data Register (HRX) Host Transmit Data Register (HTX) X:$FFEB Write Only TRANSMIT HIGH BYTE Host Transmit Data (usually loaded by program) TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE Figure B-17 Host Transmit Data Register (HTX) MOTOROLA B - 17

18 Application: HOST PROCESSOR SIDE Date: Sheet 3 of 5 Receive Request Enable DMA Off 0 = Interrupts Disabled 1 = Interrupts Enabled DMA On 0 = Host DSP 1 = DSP Host Interrupt Control Register (ICR) $0 Read/Write Reset = $00 Transmit Request Enable DMA Off 0 = Interrupts Disabled 1 = Interrupts Enabled DMA On 0 = DSP Host 1 = Host DSP Host Flags Write Only Host Mode Control 00 = DMA Off 01 = 24 Bit DMA 10 = 16 Bit DMA 11 = 8 Bit DMA Initialize (Write Only) 0 = No Action 1 = Initialize DMA HF1 HF0 TREQ RREQ Figure B-18 Interrupt Control Register (ICR) Host Vector Executive Interrupt Routine 0-63 Host Command 0 = Idle 1 = Interrupt DSP 7 INIT 6 5 HM1 HM0 0 Command Vector Register (CVR) $1 Read/Write Reset = $12 7 HC 6 5 HV HV4 HV3 HV2 HV1 HV0 Figure B-19 Command Vector Register (CVR) B - 18 MOTOROLA

19 Application: Date: Sheet 4 of 5 HOST PROCESSOR SIDE Interrupt Status Register (ISR) $2 Read/Write Reset = $06 Receive Data Register Full 0 = Wait 1 = Read Transmit Data Register Empty 0 = Wait 1 = Write Transmitter Ready 0 = Data in HI 1 = Data Not in HI Host Flags Read Only DMA Status 0 = DMA Disabled 1 = DMA Enabled Host Request 0 = HREQ Deasserted1 = HREQ Asserted 7 HREQ DMA HF3 HF2 TRDY TXDE RXDF Figure B-20 Interrupt Status Register (ISR) Exception vector number for use by MC68000 processor family vectored interrupts. Interrupt Vector Register (IVR) $3 Read/Write Reset = $0F 7 IV7 6 5 IV6 IV IV4 IV3 IV2 IV1 IV0 Figure B-21 Interrupt Vector Register (IVR) MOTOROLA B - 19

20 B - 20 MOTOROLA HOST PROCESSOR SIDE Receive Byte Registers $7, $6, $5, $4 Read Only Reset = $00 Host Receive Data (usually read by program) RECEIVE LOW BYTE RECEIVE MIDDLE BYTE RECEIVE HIGH BYTE NOT USED $7 $6 $5 $4 Figure B-22 Receive Byte Registers Transmit Byte Registers $7, $6, $5, $4 Write Only Reset = $00 Host Transmit Data (usually loaded by program) TRANSMIT LOW BYTE TRANSMIT MIDDLE BYTE TRANSMIT HIGH BYTE NOT USED $7 $6 $5 $4 Figure B- Transmit Byte Registers Application: Date: Sheet 5 of 5

21 Application: Date: Sheet 1 of 3 SCI Port C Port C Pin Control 0 = General Purpose I/O Pin 1 = Peripheral Pin Port C Control Register (PCC) X:$FFE1 Read/Write Transmitter Enable 0=Transmitter disabled 1=Transmitter enabled Idle Line Interrupt Enable 0=Idle Line Interrupts disabled 1=Idle Line Interrupts enabled Receive Interrupt Enable 0=Receive Interrupts disabled 1=Receive Interrupts enabled Transmit Interrupt Enable 0=Transmit Interrupts disabled 1=Transmit Interrupts enabled Timer Interrupt Enable 0=Timer Interrupts disabled 1=Timer Interrupts enabled SCI Timer Interrupt Rate 0= 32, 1= 1 SCI Clock Polarity 0=Clock Polarity is positive 1=Clock Polarity is negative SCI Control Register (SCR) Address X:$FFF0 Read/Write $0 0 Receiver Wakeup Enable 0=Receiver has awakened 1=Wakeup function enabled Word Select Bits = 8-bit Synchronous Data (Shift Register Mode) = Reserved = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop) = Reserved = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop) = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop) = 11-bit Multidrop (1 Start, 8 Data, Even Parity, 1 Stop) = Reserved SCKP STIR TMIE TIE Send Break 0=Send break, then revert 1=Continually send breaks Receiver Enable 0=Receiver Disabled 1=Receiver Enabled Wakeup Mode Select 0=Idle Line Wakeup 1=Address Bit Wakeup Wired-Or Mode Select 1=Multidrop 0=Point to Point CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Figure B-24 Port C Control Register (PCC) SCI Shift Direction 0 = LSB First 1 = MSB First RIE ILIE TE RE WOMS RWU WAKE SBK SSFTD WDS2WDS1 WDS0 Figure B-25 SCI Control Register (SCR) MOTOROLA B - 21

22 Application: Date: SCI Transmit/Receive Clock Selection TCM RCM TX Clock RX Clock SCLK Pin Mode 0 0 Internal Internal Output Synchronous/Asynchronous 0 1 Internal External Input Asynchronous Only 1 0 External Internal Input Asynchronous Only 1 1 External External Input Synchronous/Asynchronous Transmitter Clock Mode/Source 0=Internal clock for transmitter 1=External clock from SCLK Overrun Error Flag 0=No error 1=Overrun detected SCI Status Register (SSR) Address X:$FFF1 Read Only Reset = $ Parity Error Flag 0=No error 1=Incorrect Parity detected Framing Error Flag 0=No error 1=No Stop Bit detected Received Bit 8 0=Data 1=Address 0 Receiver Clock Mode/Source 0=Internal clock for receiver 1=External clock from SCLK R8 FE PE OR IDLE RDRF TDRE TRNE Figure B-26 SCI Status Register (SSR) Clock Divider Bits CD11-CD0 CD11 - CD0 l cyc Rate $000 l cyc /1 $001 l cyc /2 $002 l cyc / $FFE. l cyc /4095 $FFF l cyc /4096 Clock Out Divider 0=Divide clock by 16 before feed to SCLK 1=Feed clock to directly to SCLK Idle Line Flag 0=Idle not detected 1=Idle State Sheet 2 of 3 Receive Data Register Full 0=Receive Data Register full 1=Receive Data Register empty Transmitter Data Register Empty 0=Transmitter Data Register full 1=Transmitter Data Register empty Transmitter Empty 0=Transmitter full 1=Transmitter empty SCI Clock Prescaler 0= 1 1= 8 SCI Clock Control Register (SCCR) Address X:$FFF2 Read/Write 0 TCM RCM SCP COD CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 Figure B-27 SCI Clock Control Register (SCCR) B - 22 MOTOROLA

23 Application: SCI Date: Sheet 3 of 3 X0 A B C UNPACKING SCI Transmit Data Registers Address X:$FFF4 X:$FFF6 Read/Write Reset = xxxxxx X:$FFF6 X:$FFF5 X:$FFF4 NOTE: STX is the same register decoded at three different addresses. SCI Receive Data Registers Address X:$FFF4 - X:$FFF6 Read/Write Reset = xxxxxx X:$FFF6 X:$FFF5 X:$FFF4 NOTE: SRX is the same register decoded at three different addresses. STX Figure B-28 SCI Transmit Data Registers STX STX SRX PACKING SCI Transmit SR SCI Receive SR SRX TXD SRX RXD X0 A B C Figure B-29 SCI Receive Data Registers MOTOROLA B -

24 Application: SSI Port C Date: Sheet 1 of 3 Port C Control Register (PCC) X:$FFE1 Read/Write Reset = $0000 Word Length Control 00 = 8 Bits/Word 01 = 12 Bits/Word 10 = 16 Bits/Word 11 = 24 Bits/Word Prescaler Range 0 = / 1 1 = / Frame Rate Divider Control = = 32 Port C Pin Control 0 = General Purpose I/O Pin 1 = Peripheral Pin CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Figure B-30 SSI Control Register (PCC) Prescale Modulus Select SSI Control Register A (CRA) X:$FFEC Read/Write 0 PSR WL1 WL0 DC4 DC3 DC2 DC1 DC0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Figure B-31 SSI Control Register A (CRA) B - 24 MOTOROLA

25 Application: SSI Date: Sheet 2 of 3 Clock Source Direction 0 = External Clock 1 = Internal Clock Shift Direction 0 = MSB First 1 = LSB First Frame Sync Length 0 0 = Rx and Tx Same Length 1 = Rx and Tx Different Length Frame Sync Length 1 0 = Rx is Word Length1 = Rx is Bit Length Sync/Async Control 0 = Asynchronous 1 = Synchronous Gated Clock Control 0 = Continuous Clock1 = Gated Clock SSI Mode Select 0 = Normal 1 = Network Transmit Enable 0 = Disable 1 = Enable Receive Enable 0 = Disable 1 = Enable Transmit Interrupt Enable 0 = Disable 1 = Enable Receive Interrupt Enable 0 = Disable 1 = Enable Serial Control Direction Bits SCDx=0 SCDx=1 (Output) (Input) SC0 Pin Rx Clk Flag 0 SC1 Pin Rx Frame Sync Flag 1 SC2 Pin Tx Frame Sync Tx, Rx Frame Sync Output Flag x If SYN = 1 and SCD1=1 OFx SCx Pin SSI Control Register B (CRB) X:$FFED Read/Write 0 RIE TIE RE TE MOD GCK SYN FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0 Figure B-32 SSI Control Register B (CRB) MOTOROLA B - 25

26 Application: SSI Date: Sheet 3 of 3 Serial Input Flag 0 If SCD0=0 and SYN=1 latch SC0 on FS Serial Input Flag 1 If SCD1=0 and SYN=1 latch SC0 on FS Transmit Frame Sync 0 = Sync Inactive1 = Sync Active Receive Frame Sync 0 = Wait 1 = Frame Sync Occurred Transmitter Underrun Error Flag 0 = OK 1 = Error Receiver Overrun Error Flag 0 = OK 1 = Error Transmit Data Register Empty 0 = Wait 1 = Write Receive Data Register Full 0 = Wait 1 = Read SSI Status Register (SSISR) X:$FFEE (Read) Reset = $ RDF TDE ROE TUE RFS TFS IF1 IF0 Figure B-33 SSI Status Register (SSISR) SSI Status Bits B - 26 MOTOROLA

27 Application: Date: TIMER Sheet 1 of 1 Note: The first version of the DSP56002 (mask number D41G) did not have the timer/ event counter. Later versions of the DSP56002 which have different mask numbers do have the timer/event counter. This mask number can be found below the part number on each chip. Timer Control Bits 3-5 (TC0 - TC2) TC2 TC1 TC0 TIO Clock Mode GPIO Internal Timer Output Internal Timer Pulse Output Internal Timer Toggle X X Undefined Input Internal Input Width Input Internal Input Period Input External Standard Time Counter Input External Event Counter Data Input Bit 9 0 = Zero read on TIO pin 1 = One read on TIO pin Data Output Bit 10 0 =Zero written to TIO pin 1 = One written to TIO pin Timer Control and Status Register (TCSR) X:$FFDE (Read/Write) Reset = $ GPIO Bit 6 0 = TIO is Timer IO 1 = TIO is GPIO if TC2-TC0 are clear 0 Timer Status Bit 7 0 = TCSR read, or timer interrupt serviced 1 = Counter decremented to 0 Direction Bit 8 0 = TIO pin is input 1 = TIO pin is output DO DI DIR TS GPIO Timer Interrupt Enable Bit 1 0 = Interrupts Disabled 1 = Interrupts Enabled Timer Enable Bit 0 0 = Timer Disabled 1 = Timer Enabled Inverter Bit 2 0 = 0- to-1 transitions on TIO input decrement the counter 1 = 1-to-0 transitions on TIO input decrement the counter or Timer pulse inverted before it goes to TIO output Figure B-34 Timer Control and Status Register (TCSR) TC2 TC1 TC0 INV TIE TE Timer Count Register (TCR) X:$FFDF (Read/Write) Unaffected by Reset 0 Figure B-35 Timer Count Register (TCR) MOTOROLA B - 27

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