SPLD & CPLD architectures

Transcription

1 Module: Electronics & Telecomunication, 5rd year Hardware Acceleration of Telecommunication Protocols SPLD & CPLD architectures 1 PLD devices classification Source: Dataquest Logic Standard Logic ASIC Programmable Logic Devices (PLDs) SPLDs (PALs) Gate Arrays CPLDs Cell-Based ICs FPGAs Full Custom ICs Configurable Logic Blocks (CLB) Memory Look-Up Table AND-OR planes Simple gates Input / Output Blocks (IOB) Bidirectional, latches, inverters, pullup/pulldowns Interconnect or Routing Local, internal feedback, and global SPLD = Simple Prog. Logic Device PAL = Programmable Array of Logic CPLD = Complex PLD FPGA = Field Prog. Gate Array ISP In System Programmable 1

2 Agenda Programmable Logic Devices classification Simple Programmable Logic Devices (SPLD) History & backgroud, PAL, GAL devices Complex Programmable Logic Devices (CPLD) Lattice, Altera(Intel), Xilinx examples CPLD applications References WWW SPLD, CPLD manufactures (Intel from June 2017) (Intelis paying $16.7 billion in an all-cash deal to buy smaller peer Altera, the second major acquisition in the semiconductor sector in less than a week) EDA pages like 2

3 digital world before PLD (standard logic) 1961 TTL series 7400, CMOS series 4000 more then 200 types (gates/flip flops/registers/ decoders/encoders/ multiplexers and many others) SPLD Simple Programmable Logic Devices PAL (Programmable Array Logic, AMD Vantis) PLA (Programmable Logic Array) GAL (Generic Array Logic, Lattice) 3

4 Canonical form PAL device basic structure PAL device programmable AND matrix and fixed OR matrix bipolar technology fuses John Birkner and H.T. Chua of Monolithic Memories worked with Andy Chan to introduce a more streamlined architecture they called Programmable Array Logic (PAL) in

5 PAL device logic function example Simple PLD PAL (Programmable Array Logic) 16L8, 16R4, 16R6, 16R8 GAL (Generic Array Logic) 16V8, 20V8, 22V10, 26V12 PLA (Programmable Logic Array) 5

6 Simple PLD PAL16L8 Block diagram and internal architecture PAL devices - families 12,14,16,20 Bipolar technology One time programmable by fuse burning Symbol PAL xx Y z xx inputs count Y - L low active logic H high active logic C complemetary logic R synchronous flip flops RA asynchronous flip flops X, A extra arithmetic circuitry S shared terms version z - outputs count (registered or combinatorial) 6

7 GAL - Generic Array Logic devices Year 1985 Technology E 2 CMOS Many times (~10k and more...) programmable Clearing time ~100ms GAL16V8 GAL 20V10 - world wide standard GAL ISP (In System Programmable) HDPLD High Density PLD 7

8 Simple PLD GAL22V10 example GAL devices term number not equal for each pin Simple PLD GAL22V10 GAL 22V10 D flip flop inputs: Asynchronic Reset (AR) Synchronic Set (SR) 8

9 GAL22V10 macrocell SPLD still on the market Companies: Atmel, Texas Instruments 2017 Ready to buy SPLD for example DigiKey webstore 9

10 CPLD general architecture CPLD Macrocells (PAL like) Commutation matrices Technology:CMOS (Re)Configuration: EPROM (UV + version OTP) EEPROM FLASH (ISP) CPLD- Predictable timing CPLD Complex Programmable Logic Devices Altera (CPLD leader?) Atmel (support for older devices. 22V10 + military std) Lattice (vice leader? CPLD..) Xilinx (CPLD as the FPGA portfolio support) 10

11 CPLD Xilinx CPLD Xilinx XC95xx series 11

12 CPLD Xilinx XC95xx series CPLD Xilinx XC95xx series Optimized for high-performance 3.3V systems - 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz - Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package) - Pb-free available for all packages - Lower power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS FastFLASH technology Advanced system features - In-system programmable - Superior pin-locking and routability with FastCONNECT II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin with local inversion - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Supports hot-plugging capability - Full IEEE Standard boundary-scan (JTAG) support on all devices Four pin-compatible device densities - 36 to 288 macrocells, with 800 to 6400 usable gates Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - 10,000 program/erase cycles endurance rating - 20 year data retention Pin-compatible with 5V core XC9500 family in common package footprints 12

13 CPLD Xilinx CoolRunner CPLD from Lattice The Do-it-All PLD - MachXO2 Offers an unprecedented mix of low cost, low power and high system integration for system and consumer designs Most Versatile Non-Volatile PLD - MachXO Combines FPGA flexibility with CPLD performance, instant-on and high pin to logic ratio Ultra Low Power CPLD - ispmach 4000ZE As low as 10µA standby current, packages as small as 4x4 mm, 5V-tolerant I/Os + Mature devices (PAL, PALCE, GAL, ispgdx, isplsi 1k..8k,ORCA,MACH 1,2,4) 13

14 Lattice ispmach4000 CPLD SuperFAST Performance 2.5 ns tpd Pin-to-Pin Delay 400 MHz System Performance Industry s Lowest Power Consumption 1.8V Core for Low Dynamic Power Low Static Current ma (1.8V Device Family) ma (2.5V and 3.3V Device Families) Multiple Temperature Range Options Commercial: 0 to 70º C TA (Ambient) Industrial: -40 to 85ş C TA (Ambient) Automotive: -40 to 125ş C TA (Ambient) Ease of Design Excellent First-Time Fit and Refit Capability 4 Global Clocks 36 Inputs per Logic Block Up to 80 Product Terms (PT) per Output ORP for Pin Locking Density Migration Flexible Control, Clocking and OE Fast, SpeedLocking, and Wide PT Paths 5V Tolerant Inputs and I/O Easy System Integration Operation with 1.8V, 2.5V and 3.3V Supplies 1.8V, 2.5V, 3.3V I/O Support IEEE 1532 In-System Programmable (ISP ) IEEE Boundary Scan Test Open Drain Output for Flexible Bus Interface Capability Programmable Pull-Up or Bus-Keeper Inputs Hot Socketing Capability 3.3V PCI Compatible Programmable Output Slew Rate Lead-free Package Options Lattice ispmach4000 CPLD 14

15 Lattice ispmach4000 CPLD Altera CPLD Układy MAX V, MAX II, MAX Software Quartus II (free for CPLD...) 15

16 CPLD Altera series MAX V Feature Summary The following list summarizes the MAX V device family features: Low-cost, low-power, and non-volatile CPLD architecture Instant-on (0.5 ms or less) configuration time Standby current as low as 25 μa and fast power-down/reset operation Fast propagation delay and clock-to-output times Internal oscillator Emulated RSDS output support with a data rate of up to 200 Mbps Emulated LVDS output support with a data rate of up to 304 Mbps Four global clocks with two clocks available per logic array block (LAB) User flash memory block up to 8 Kbits for non-volatile storage with up to 1000 read/write cycles Single 1.8-V external supply for device core MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, andprogrammable pull-up resistors Schmitt triggers enabling noise tolerant inputs (programmable per pin) CPLD Altera MAX V - architecture The CFM block provides the non-volatile storage for all of the SRAM configuration information. The CFM automatically downloads and configures the logic and I/O at power-up, providing instant-on operation. A portion of the flash memory within the MAX V device is partitioned into a small block for user data. This user flash memory (UFM) block provides 8,192 bits of general-purpose user storage. The UFM provides programmable port connections to the logic array for reading and writing. 16

17 CPLD Altera MAX V - connections LE grouped in 10 at Logic Array Block Connection buses rows, columns Direct connections to LAB Direct connections to I/O Global clk networks CPLD Altera MAX V I/O blocks and LE I/O block LVTTL, LVCMOS, LVDS, and RSDS I/O standards JTAG boundary-scan test (BST) support programmable drive strength control weak pull-up resistors during power-up and in system programming tri-state buffers with individual output enable bus-hold circuitry programmable pull-up resistors in user mode open-drain outputs Schmitt trigger inputs, programmable input delay Each LE contains: four-input LUT, programmable register (D, T, JK, or SR operation) carry chain with carry-select capability. supports dynamic single-bit addition or subtraction mode clock enable, preset, asynchronous load, and asynchronous data. 17

18 CPLD applications Lattice marketing data CPLD applications Xilinx marketing data This Chapter contains the following topics: IrDA and UART Design in a CoolRunner CPLD Serial ADC Interface Using a CoolRunner CPLD Wireless Transceiver for the CoolRunner CPLD CoolRunner-II Smart Card Reader CoolRunner-II CPLD I2C Bus Controller Implementation CoolRunner-II Serial Peripheral Interface Master Design of a Digital Camera with CoolRunner-II CPLDs CompactFlash Card Interface for CoolRunner-II CPLDs Interfacing to Mobile SDRAM with CoolRunner-II CPLDs An SMBus/I2C-Compatible Port Expander Driving LEDs with Xilinx CPLDs CoolRunner-II CPLDs in Cell Phone Handsets/Terminals Implementing Keypad Scanners with CoolRunner-II Level Translation Using Xilinx CoolRunner-II CPLDs CoolRunner-II Character LCD Module Interface Using Xilinx CPLDs to Interface to a NAND Flash Memory Device Cell Phone Security Demoboard On The Fly Reconfiguration Technique Using CoolRunner-II with OMAP, XScale, i.mx & Other Chipsets Connecting Intel PXA27x Processors to Hard-Disk Drives with a CoolRunner-II CPLD A Low-Power IDE Controller Design Using a CoolRunner-II CPLD Using a Xilinx CoolRunner-II CPLD as a Data Stream Switch Supporting Multiple SD Devices with CoolRunner-II CPLDs 18

19 CPLD applications Altera marketing data Thank you! Rajda & Kasperek 2012 Katedra Elektroniki AGH 38 19